700MHz, Differential-to-3.3V LVPECL 8735BI-21 Zero Delay Clock Generator DATA SHEET General Description Features The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL One differential 3.3V LVPECL output pair, one differential feedback clock generator. The CLK, nCLK pair can accept most standard output pair differential input levels. The 8735BI-21 has a fully integrated PLL and Differential CLK, nCLK input pair can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference CLK, nCLK pair can accept the following differential input levels: divider, feedback divider and output divider are each programmable, LVDS, LVPECL, LVHSTL, HCSL thereby allowing for the following output-to-input frequency ratios: Output frequency range: 31.25MHz to 700MHz 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve zero delay between the input clock and the output Input frequency range: 31.25MHz to 700MHz clocks. The PLL SEL pin can be used to bypass the PLL for system VCO range: 250MHz to 700MHz test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 External feedback for zero delay clock regeneration with Pin Assignment configurable frequencies Cycle-to-cycle jitter: 50ps (maximum) 1 20 CLK nc 3.3V supply voltage 2 19 nCLK SEL1 3 18 MR SEL0 -40C to 85C ambient operating temperature 4 17 V V CC CC Available in RoHS compliant package 5 16 nFB IN PLL SEL 6 15 FB IN V CCA 7 14 SEL2 SEL3 8 13 V V EE CCO Block Diagram 12 nQFB 9 Q 10 11 PLL SEL QFB nQ 1, 2, 4, 8, Q 8735BI-21 0 16, 32, 64 nQ 20-pin, 7.5mm x 12.8mm X 2.3MM SOIC Package CLK QFB 1 nQFB nCLK PLL 32 31 30 29 28 27 26 25 8:1, 4:1, 2:1, 1:1, FB IN 1:2, 1:4, 1:8 1 24 SEL0 V CCO nFB IN 2 SEL1 23 nc 3 22 nc Q 4 21 nc nQ SEL0 8735BI-21 5 CLK 20 SEL1 QFB 6 SEL2 nCLK 19 nQFB SEL3 nc 7 18 nc MR 8 MR 17 V cco 9 10 11 12 13 14 15 16 32-pin, 5mm x 5mm X 0.925MM VFQFN Package 8735BI-21 REVISION 1 1/27/15 1 2015 Integrated Device Technology, Inc. V nc CC nc V CC nFB IN PLL SEL FB IN V CCA SEL2 SEL3 V V EE EE nc nc nc nc8735BI-21 DATA SHEET Pin Descriptions and Characteristics 1 Table 1. Pin Descriptions Name Type Description CLK Input Pulldown Non-inverting differential clock input. nCLK Input Pullup Inverting differential clock input. nFB IN Input Pullup Feedback input to phase detector for regenerating clocks with zero delay. Connect to nQFB. FB IN Input Pulldown Feedback input to phase detector for regenerating clocks with zero delay. Connect to QFB. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the MR Input Pulldown true outputs Q and QFB to go low and the inverted outputs nQ and nQFB to go high. When LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. SEL0, SEL1, Determines output divider values in Table 3. Input Pulldown SEL2, SEL3 LVCMOS / LVTTL interface levels. Selects between the PLL and reference clock as the input to the dividers. When LOW, PLL SEL Input Pullup selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. nQ, Q Output Differential feedback outputs. LVPECL interface levels. nQFB, QFB Output Differential feedback outputs. LVPECL interface levels. V Power Negative supply. EE V Power Core supply. CC V Power Analog supply. CCA V Power Output supply. CCO NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance IN, nIN 4 pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY 2 REVISION 1 1/27/15 CLOCK GENERATOR