Low Skew, 1/2 Differential-to-3.3V 8737-11 LVPECL Clock Generator DATASHEET GENERAL DESCRIPTION FEATURES The 8737-11 is a low skew, high performance 2 divide by 1 differential 3.3V LVPECL outputs Differential-to-3.3V LVPECL Clock Generator/Divider. The 2 divide by 2 differential 3.3V LVPECL outputs 8737-11 has two selectable clock inputs. The CLK, nCLK Selectable differential CLK, nCLK or LVPECL clock inputs pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL CLK, nCLK pair can accept the following differential input levels.The clock enable isinternally synchronized to input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL eliminate runt pulses on theoutputs during asynchronous as- PCLK, nPCLK supports the following input types: sertion/deassertion of the clock enable pin. LVPECL, CML, SSTL Guaranteed output and part-to-part skew characteristics make Maximum output frequency: 650MHz the 8737-11 ideal for clock distribution applications demanding Translates any single ended input signal (LVCMOS, LVTTL, well de ned performance and repeatability. GTL) to LVPECL levels with resistor bias on nCLK input Output skew: 60ps (maximum) Part-to-part skew: 200ps (maximum) Bank skew: Bank A - 20ps (maximum), Bank B - 35ps (maximum) Additive phase jitter, RMS: 0.04ps (typical) Propagation delay: 1.7ns (maximum) 3.3V operating supply 0C to 70C ambient operating temperature Lead-Free package RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT QA0 VEE 1 20 CLK EN 2 19 nQA0 VCC CLK SEL 3 18 CLK 4 17 QA1 5 16 nQA1 nCLK QB0 PCLK 6 15 nPCLK 7 14 nQB0 VCC nc 8 13 MR 9 12 QB1 10 11 nQB1 VCC 8737-11 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View 8737-11 REVISION C 2/13/15 1 2015 Integrated Device Technology, Inc.8737-11 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Power Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. 8 nc Unused No connect. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs QXx to go low and the inverted outputs 9 MR Input Pulldown nQXx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 10, 13, 18 V Power Positive supply pins. CC 11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN LOW SKEW, 1/2 2 REVISION C 2/13/15 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR