Low Skew 1/2 8737I-11 Differential-to- 3.3V LVPECL Clock Generator DATA SHEET GENERAL DESCRIPTION FEATURES The 8737I-11 is a low skew, high performance Two divide by 1 differential 3.3V LVPECL outputs Differential-to-3.3V LVPECL ClockGenerator/Divider. Two divide by 2 differential 3.3V LVPECL outputs The 8737I-11 has two selectable clock inputs. The CLK, Selectable differential CLK, nCLK or LVPECL clock inputs nCLK pair can acceptmost standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CLK, nCLK pair can accept the following differential CML, or SSTL input levels.The clock enable is internally input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL synchronized to eliminate runt pulses on the outputs PCLK, nPCLK supports the following input types: during asynchronous assertion/deassertion of the clock LVPECL, CML, SSTL enable pin. Maximum output frequency: 650MHz Guaranteed output and part-to-part skew characteristics Translates any single ended input signal (LVCMOS, LVTTL, make the 8737I-11 ideal for clock distribution applications GTL) to LVPECL levels with resistor bias on nCLK input demanding well de ned performance and repeatability. Output skew: 75ps (maximum) Part-to-part skew: 300ps (maximum) Bank skew: Bank A - 30ps (maximum) Bank B - 45ps (maximum) 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free RoHS-compliant package BLOCK DIAGRAM PIN ASSIGNMENT 8737I-11 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View 8737I-11 REVISION C 7/16/15 1 2015 Integrated Device Technology, Inc.8737I-11 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Power Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. 8 nc Unused No connect. Active HIGH Master Reset. When logic HIGH, the internal dividers 9 MR Input Pulldown are reset. When LOW, the Master Reset is disabled. LVCMOS / LVTTL interface levels. 10, 13, 18 V Power Positive supply pins. CC 11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN LOW SKEW 1/2 2 REVISION C 7/16/15 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR