Differential-to-3.3V LVPECL 873996 Zero Delay/Multiplier/Divider DATA SHEET GENERAL DESCRIPTION FEATURES Six differential 3.3V LVPECL outputs The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase Selectable differential clock inputs noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL critical. The device receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with zero delay. Input clock frequency range: 49MHz to 213.33MHz The output divider and feedback divider selections also allow for Output clock frequency range: 49MHz to 640MHz frequency multiplication or division. VCO range: 490MHz to 640MHz The 873996 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of a failure (input External feedback for zero delay clock regeneration clock stuck LOW or HIGH for at least 1 period), INP BAD for that with con gurable frequencies clock will be set HIGH. If that clock is the primary clock, the DCS will Output skew: 100ps (maximum) switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. RMS phase jitter (1.875MHz - 20MHz): 0.6ps (typical) assum- ing a low phase noise reference clock input The low jitter characteristics combined with input clock monitor-ing and automatic switching from bad to good input clocks make the 3.3V supply voltage 873996 an ideal choice for mission critical applications that utilize 0C to 70C ambient operating temperature 1G or 10G Ethernet or 1G/4G/10G Fibre Channel. Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 873996 REVISION A 11/10/15 1 2015 Integrated Device Technology, Inc.873996 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Selects between the PLL and reference clock as the input to the di- 1 PLL SEL Input Pullup viders. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels. Active LOW Master Reset. When logic LOW, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs 2 nMR Input Pullup nQx to go high. When logic HIGH, the internal dividers and the out- puts are enabled. LVCMOS / LVTTL interface levels. When HIGH-to-LOW, resets the input bad ags and aligns CLK INDI- 3 nINIT Input Pullup CATOR to SEL CLK. LVCMOS / LVTTL interface levels. 4, 17 V Power Negative supply pins. EE 5 CLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 6 nCLK0 Input Inverting differential clock input. V /2 default when left oating. CC Pulldown 7 CLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 8 nCLK1 Input Inverting differential clock input. V /2 default when left oating. CC Pulldown 9 EXT FB Input Pulldown Differential external feedback. Pullup/ 10 nEXT FB Input Differential external feedback. V /2 default when left oating. CC Pulldown Selects the primary reference clock. When LOW, selects CLK0 as the 11 SEL CLK Input Pulldown primary clock source. When HIGH, selects CLK1 as the primary clock source. LVCMOS / LVTTL interface levels. Bandwidth control pin. LVCMOS / LVTTL interface levels. Pullup/ Float (default) = Medium Bandwidth (~800kHz), 12 BW Input Pulldown 1 = High Bandwidth (~2000kHz), 0 = Low Bandwidth (~400kHz). 13, 47 V Power Core supply pins. CC Bank B output divider control pins 14, 15, 16 NB0, NB1, NB2 Input Pullup LVCMOS / LVTTL interface levels. Bank A output divider control pins 18, 19, 20 NA0, NA1, NA2 Input Pullup LVCMOS / LVTTL interface levels. 21, 28 V Power Output supply voltage for B Bank outputs. CCO B 22, 23 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 24, 25 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 26, 27 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 29, 36 V Power Output supply voltage for A Bank outputs. CCO A 30, 31 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 32, 33 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 34, 35 nQA0, QA0 Output Differential output pair. LVPECL interface levels. 37 V Power Output supply voltage for FB output. CCO FB 38, 39 QFB, nQFB Output Feedback outputs. LVPECL interface levels. 40 V Power Analog supply pin. CCA 41, 42, 43 NFB0, NFB1, NFB2 Input Pullup Feedback divider control pins. LVCMOS / LVTTL interface levels. Clock indicator pin. When LOW, CLK0, nCLK0 is selected. When 44 CLK INDICATOR Output HIGH, CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Continued on next page... DIFFERENTIAL-TO-3.3V LVPECL 2 REVISION A 11/10/15 ZERO DELAY/MULTIPLIER/DIVIDER