2.5V Differential LVDS Clock Divider 874208I and Fanout Buffer DATA SHEET General Description Features The 874208I is a high-performance differential LVDS clock divider One differential input reference clock and fanout buffer. The device is designed for the frequency division Differential pair can accept the following differential input and signal fanout of high-frequency, low phase-noise clocks. The levels: LVDS, LVPECL, CML 874208I is characterized to operate from a 2.5V power supply. Integrated input termination resistors Guaranteed output-to-output and part-to-part skew characteristics Eight LVDS outputs make the 874208I ideal for those clock distribution applications Selectable clock frequency division of 1, 2, 4 and 8 demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the Maximum input clock frequency: 500MHz reference source easy and reduce passive component count. Each LVCMOS interface levels for the control inputs output can be individually enabled or disabled in the high-impedance 2 Internal regulator for improved noise immunity state controlled by a I C register. On power-up, all outputs are 2 enabled. Individual output enable/disabled by I C interface Output skew: 28ps Additive Phase Jitter, RMS: 0.168ps (typical), 125MHz Low additive phase jitter Full 2.5V supply voltage Available in Lead-free (RoHS 6) package -40C to 85C ambient operating temperature Block Diagram Pin Assignment Q0 nQ0 32 31 30 29 28 27 26 25 Q1 1 ADR1 24 FSEL0 nQ1 GND 2 23 GND f REF Q0 3 nQ7 22 IN Q2 1, 2, nIN nQ2 Q7 4, 8 nQ0 4 21 Q1 nQ6 5 20 50 50 Q3 nQ1 6 Q6 19 V nQ3 T GND 7 GND 18 Pulldown (2) Q4 FSEL 1:0 VDDO 8 VDDO 17 9 10 11 12 13 14 15 16 nQ4 Q5 nQ5 ICS874208I Pullup 2 SDA I C Pullup 32 Lead VFQFN 8 Q6 SCL Pulldown (2) 5mm x 5mm x 0.925mm package body nQ6 ADR 1:0 2 K Package Top View Q7 nQ7 REVISION A 9/18/14 1 2014 Integrated Device Technology, Inc. Q2 ADR0 nQ2 SCL Q3 SDA nQ3 VDD Q4 nIN nQ4 VT Q5 IN nQ5 FSEL1874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, ADR1, 2 Input Pulldown I C Address inputs. LVCMOS/LVTTL compatible interface levels. 32 ADR0 2, 7, 18, 23 GND Power Power supply ground. 3, 4 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 5, 6 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 8, 17 V Power Output power supply pins. DDO 9, 10 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 11, 12 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. 13, 14 Q4, nQ4 Output Differential output pair 4. LVDS interface levels. 15, 16 Q5, nQ5 Output Differential output pair 5. LVDS interface levels. 19, 20 Q6, nQ6 Output Differential output pair 6. LVDS interface levels. 21, 22 Q7, nQ7 Output Differential output pair 7. LVDS interface levels. FSEL0, Frequency divider select controls. See Table 3A for function. 24, 25 Input Pulldown FSEL1 LVCMOS/LVTTL interface levels. 26 IN Input Non-inverting differential clock input. Termination Input for termination. Both IN and nIN inputs are internally terminated 50 to 27 V T input this pin. See input termination information in the applications section. 28 nIN Input Inverting differential clock input. 29 V Power Power supply pins. DD 2 I C Data Input/Output. Input: LVCMOS/LVTTL interface levels. 30 SDA I/O Pullup Output: open drain. 2 31 SCL Input Pullup I C clock input. LVCMOS/LVTTL compatible interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP REVISION A 9/18/14 2 2014 Integrated Device Technology, Inc.