Q 8745B-21 1:1 Differential-to-LVDS Zero Delay Clock Generator DATA SHEET General Description Features The 8745B-21 is a highly versatile 1:1 LVDS Clock Generator. The One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 8745B-21 has a fully integrated PLL and can be configured as zero One differential feedback output pair delay buffer, multiplier or divider, and has an output frequency range Differential CLK, nCLK input pair of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the CLKx, nCLKx pair can accept the following differential following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL 1:8. The external feedback allows the device to achieve zero delay Output frequency range: 31.25MHz to 700MHz between the input clock and the output clock. The PLL SEL pin can Input frequency range: 31.25MHz to 700MHz be used to bypass the PLL for system test and debug purposes. In VCO range: 250MHz to 700MHz bypass mode, the reference clock is routed around the PLL and into the internal output dividers. External feedback for zero delay clock regeneration with configurable frequencies Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Cycle-to-cycle jitter: 30ps (maximum) Output skew: 35ps (maximum) Static phase offset: 25ps 125ps Full 3.3V supply voltage 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Pullup PLL SEL CLK 1 20 SEL1 Q nCLK 2 19 SEL0 1, 2, 4, 8, nQ 0 MR 3 18 VDD 16, 32, 64 nFB IN 4 17 PLL SEL PulldownPulldown CLK FB IN 5 16 VDDA QFB 1 PullupPullup nCLK SEL2 6 15 SEL3 nQFB VDDO 7 14 GND nQFB 8 13 PLL QFB 9 12 nQ GND 10 11 VDDO 8:1, 4:1, 2:1, 1:1, Pulldown FB IN 1:2, 1:4, 1:8 8745B-21 Pullup nFB IN 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Pulldown Top View SEL0 Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR 8745B-21 Rev D 2/17/15 1 2015 Integrated Device Technology, Inc.8745B-21 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output nQ to go high. 3 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Inverting differential feedback input to phase detector for regenerating clocks with 4 nFBIN Input Pullup Zero Delay. Non-inverted differential feedback input to phase detector for regenerating clocks 5 FBIN Input Pulldown with Zero Delay. 6, 15, SEL2, SEL3, Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 19, 20 SEL0 SEL1 7, 11 V Power Output supply pins. DDO 8, 9 nQFB/QFB Output Differential feedback output pair. LVDS interface levels. 10, 14 GND Power Power supply ground. 12, 13 nQ/Q Output Differential output pair. LVDS interface levels. 16 V Power Analog supply pin. DDA PLL select. Selects between the PLL and reference clock as the input to the 17 PLL SEL Input Pullup dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. 18 V Power Core supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 2 Rev D 2/17/15