1:5 Differential-to-LVDS Zero Delay ICS8745BI Clock Generator DATA SHEET General Description Features The ICS8745BI is a highly versatile 1:5 LVDS Clock Five differential LVDS outputs designed to meet or exceed the requirements of ANSI TIA/EIA-644 ICS Generator and a member of the HiPerClockS family HiPerClockS of High Performance Clock Solutions from IDT. The Selectable differential clock inputs ICS8745BI has a fully integrated PLL and can be CLKx, nCLKx pairs can accept the following differential configured as zero delay buffer, multiplier or divider, input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL and has an output frequency range of 31.25MHz to 700MHz. The Output frequency range: 31.25MHz to 700MHz Reference Divider, Feedback Divider and Output Divider are each Input frequency range: 31.25MHz to 700MHz programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external VCO range: 250MHz to 700MHz feedback allows the device to achieve zero delay between the input External feedback for zero delay clock regeneration clock and the output clocks. The PLL SEL pin can be used to with configurable frequencies bypass the PLL for system test and debug purposes. In bypass Programmable dividers allow for the following output-to-input mode, the reference clock is routed around the PLL and into the frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 internal output dividers. Cycle-to-cycle jitter: 30ps (maximum) Output skew: 40ps (maximum) Static phase offset: 25ps 125ps Full 3.3V supply voltage -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram Pin Assignment Q0 nQ0 Pullup PLL SEL Q1 nQ1 1, 2, 4, 8, 32 31 30 29 28 27 26 25 0 16, 32, 64 PulldownPulldown CLK0 Q2 SEL0 1 Q3 24 PullupPullup 0 nCLK0 nQ2 SEL1 2 23 nQ3 1 Pulldown Q3 CLK1 1 CLK0 3 VDDO Pullup 22 nQ3 nCLK1 4 Q2 nCLK0 21 PLL Q4 Pulldown CLK SEL nQ4 CLK1 nQ2 5 20 8:1, 4:1, 2:1, 1:1, nCLK1 6 GND 19 Pulldown FB IN 1:2, 1:4, 1:8 Pullup CLK SEL 7 Q1 18 nFB IN MR 8 17 nQ1 9 10 11 12 13 14 15 16 Pulldown SEL0 Pulldown SEL1 ICS8745BI Pulldown SEL2 32-Lead LQFP 7mm x 7mm x 1.4mm Pulldown package body SEL3 Pulldown Top View MR ICS8745BYI REVISION D JUNE 11, 2009 1 2009 Integrated Device Technology, Inc. VDD VDD nFB IN PLL SEL FB IN VDDA SEL2 SEL3 GND VDDO nQ0 Q4 Q0 nQ4 VDDO GNDICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1, 2, SEL0, SEL1, Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 12, 29 SEL2 SEL3 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. Clock select input. When HIGH, selects CLK1,nCLK1. When LOW, selects CLK0, 7 CLK SEL Input Pulldown nCLK0. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 8 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 9, 32 V Power Core supply pins. DD Inverting differential feedback input to phase detector for regenerating clocks with 10 FBIN Input Pullup Zero Delay. Non-inverted differential feedback input to phase detector for regenerating clocks 11 FBIN Input Pulldown with Zero Delay. 13, 19, 25 GND Power Power supply ground. 14, 15 nQ0/Q0 Output Differential output pair. LVDS interface levels. 16, 22, 28 V Power Output supply pins. DDO 17, 18 nQ1/Q1 Output Differential output pair. LVDS interface levels. 20, 21 nQ2/Q2 Output Differential output pair. LVDS interface levels. 23, 24 nQ3/Q3 Output Differential output pair. LVDS interface levels. 26, 27 nQ4/Q4 Output Differential output pair. LVDS interface levels. 30 V Power Analog supply pin. DDA PLL select. Selects between the PLL and reference clock as the input to the 31 PLL SEL Input Pullup dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS8745BYI REVISION D JUNE 11, 2009 2 2009 Integrated Device Technology, Inc.