Low Voltage/Low Skew, 1:4 PCI/PCI-X 87604I Zero Delay Clock Generator DATA SHEET GENERAL DESCRIPTION FEATURES The 87604I is a 1:4 PCI/PCI-X Clock Generator. The 87604I has Fully integrated PLL a selectable REF IN or crystal input. The REF IN input accepts Four LVCMOS/LVTTL outputs, 15 typical output impedance LVCMOS or LVTTL input levels. The 87604I has a fully integrated Selectable crystal oscillator interface or PLL along with frequency con gurable clock and feedback outputs LVCMOS/LVTTL REF IN clock input for multiply-ing and regenerating clocks with zero delay. The Maximum output frequency: 166.67MHz PLLs VCO has an operating range of 250MHz - 500MHz, allowing this device to be used in a variety of general purpose clocking Maximum crystal input frequency: 38MHz applications. For PCI/PCI-X applications in particular, the VCO Maximum REF IN input frequency: 41.67MHz frequency should be set to 400MHz. This can be accomplished Individual banks with selectable output dividers for by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the generating 33.333MHz, 66.66MHz, 100MHz and reference clock or crystal input and by selecting 12, 16, 20, or 133.333MHz 24, respectively as the feedback divide value. The divider on the Separate feedback control for generating PCI / PCI-X output bank can then be con gured to generate 33.33MHz (12), frequencies from a 16.66MHz or 20MHz crystal, or 25MHz 66.66MHz (6), 100MHz (4), or 133.33MHz (3). or 33.33MHz reference frequency The 87604I is characterized to operate with its core VCO range: 250MHz to 500MHz supply at 3.3V and the bank supply at 3.3V or 2.5V. The Cycle-to-cycle jitter: 120ps (maximum) 87604I is packaged in a small 6.1mm x 9.7mm TSSOP Period jitter, RMS: 20ps (maximum) body, making it ideal for use in space-constrained applications. Output skew: 65ps (maximum) Static phase offset: 160ps 160ps Voltage Supply Modes: V /V /V DD DDA DDO 3.3/3.3/3.3 3.3/3.3/2.5 -40C to 85C ambient operating temperature BLOCK DIAGRAM Available in lead-free (RoHS 6) package PIN ASSIGNMENT VDD 1 28 FBDIV SEL1 FB IN 27 FBDIV SEL0 2 GND DIV SEL1 26 3 FB OUT DIV SEL0 4 25 REF OUT nc 24 5 VDDO 6 23 MR Q3 nc 7 22 Q2 GND 8 21 GND 20 GND 9 Q1 10 19 nc Q0 11 18 REF IN VDDO 12 XTAL OUT 17 PLL SEL 13 16 XTAL IN VDDA 14 15 XTAL SEL 87604I 28-Lead TSSOP, 240MIL 6.1mm x 9.7mm x 0.92mm body package G Package Top View 87604I REVISION B 11/11/15 1 2015 Integrated Device Technology, Inc.87604I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Core supply pin. DD Feedback input to phase detector for generating clocks with 2 FB IN Input Pulldown zero delay. LVCMOS / LVTTL interface levels. 3, 9, 20, 21 GND Power Power supply ground. 4 FB OUT Output Feedback output. Connect to FB IN. LVCMOS / LVTTL interface levels. 5 REF OUT Output Reference clock output. LVCMOS / LVTTL interface levels. 6, 12 V Power Output supply pin DDO 7, 8, Q3, Q2, Clock outputs. 15 typical output impedance. Output 10, 11 Q1, Q0 LVCMOS / LVTTL interface levels. Selects between PLL and bypass mode. When HIGH, selects PLL. 13 PLL SEL Input Pullup When LOW, selects reference clock. LVCMOS / LVTTL interface levels. 14 V Power Analog supply pin. See Applications Note for ltering. DDA Selects between crystal oscillator or reference clock as the PLL reference 15 XTAL SEL Input Pullup source. Selects XTAL inputs when HIGH. Selects REF IN when LOW. LVCMOS / LVTTL interface levels. 16, XTAL IN, Crystal oscillator interface. XTAL IN is the input. Input 17 XTAL OUT XTAL OUT is the output. 18 REF IN Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels. 19, 22, 24 nc Unused No connect. Active HIGH Master Reset. When logic HIGH, the internal dividers 23 MR Input Pulldown are reset causing the outputs go low. When logic LOW, the internal divid- ers and the outputs are enabled. LVCMOS / LVTTL interface levels. 25, DIV SEL0, Selects divide value for clock outputs as described in Table 3. Input Pulldown 26 DIV SEL1 LVCMOS / LVTTL interface levels. 27, FBDIV SEL0, Selects divide value for reference clock output and feedback output. Input Pulldown 28 FBDIV SEL1 LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V , V , V = 3.465V 9 pF Power Dissipation Capacitance DD DDA DDO C PD (per output) NOTE 1 V , V = 3.465V V = 2.625V 11 pF DD DDA DDO R Output Impedance 15 OUT Low Voltage/Low Skew, 1:4 PCI/PCI-X 2 REVISION B 11/11/15 Zero Delay Clock Generator