GND
QD2
QB
VDDO
VDDO
QD3
QA
GND
GND
QD4
CLK
VDDO
PLL_SEL
MR/nOE
XTAL_OUT
CLK_SEL
Low Skew, 1-to-9 87950I
LVCMOS / LVTTL Clock Multiplier
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES NOVEMBER 2, 2016 DATA SHEET
GENERAL DESCRIPTION FEATURES
Fully integrated PLL
The 87950I is a low voltage, low skew 1-9 LVCMOS/LVTTL
Clock Generator. With output frequencies up to 250MHz the
9 single ended 3.3V LVCMOS/LVTTL outputs
87950I is targeted for high performance clock applications.
Along with a fully integrated PLL the 87950I contains frequency Selectable CLK or single ended crystal inputs
con gurable outputs.
Maximum output frequency: 250MHz
Maximum VCO range: 240MHz to 500MHz
Cycle-to-cycle jitter: 100 (typical)
Output skew: 375ps (maximum) all outputs @ same frequen-
PIN ASSIGNMENT
cy
3.3V operating supply
-40C to 85C ambient operating temperature
32 31 30 29 28 27 26 25
VDDA 24
1 QC0
Available in lead-free (RoHS 6) package
FBDIV_SEL 23
2 VDDO
For functional replacement part use 87973i
87950I
DIV_SELA 22
3 QC1
32-Lead LQFP
DIV_SELB 21
4 GND
7mm x 7mm x 1.4mm
DIV_SELC 20
5 QD0
package body
DIV_SELD 19
6 VDDO
Y package
GND 18
7 Top View QD1
XTAL_IN
17 GND
8
9 10 11 12 13 14 15 16
BLOCK DIAGRAM
Pulldown
DIV_SELA
Pulldown
PLL_SEL
Pulldown
CLK
Pulldown
CLK_SEL
1
2
0
0
0
QA
PHASE VCO
XTAL_IN 4
OSC DETECTOR 240-500MHz 1
1
XTAL_OUT
8
0
LPF
QB
1
8/16
Pulldown
FBDIV_SEL
0
Pulldown
DIV_SELB
QC0
QC1
1
Pulldown
DIV_SELC
Pulldown
MR/nOE
QD0
Power-On Reset
0
QD1
1
QD2
QD3
Pulldown
DIV_SELD
QD4
REVISION C 11/6/15 1 2015 Integrated Device Technology, Inc.87950I DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1V Power Analog supply pin.
DDA
Selects divide value for Bank feedback output as described in
2 FBDIV_SEL Input Pulldown
Table 3E. LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
3 DIV_SELA Input Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D.
4 DIV_SELB Input Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C outputs as described in Table 3D.
5 DIV_SELC Input Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for Bank D outputs as described in Table 3D.
6 DIV_SELD Input Pulldown
LVCMOS / LVTTL interface levels.
7, 13, 17,
GND Power Power supply ground.
21, 25, 29
8, XTAL_IN, XTAL_ Crystal oscillator interface. XTAL_IN is the input,
Input
9 OUT XTAL_OUT is the output.
Active High Master Reset. Active Low Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are tri-stated (HiZ). When
10 MR/nOE Input Pulldown
logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
11, 15, 19,
V Power Output supply pins.
DDO
23, 27
12, 14, QD4, QD3, Bank D clock outputs. 7 typical output impedance.
Output
16, 18, 20 QD2, QD1, QD0 LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7 typical output impedance.
22, 24 QC1, QC0 Output
LVCMOS / LVTTL interface levels.
Bank B clock output. 7 typical output impedance.
26 QB Output
LVCMOS / LVTTL interface levels.
Bank A clock output. 7 typical output impedance.
28 QA Output
LVCMOS / LVTTL interface levels.
30 CLK Input Pulldown LVCMOS / LVTTL phase detector reference clock input.
Selects between the PLL and the reference clock as the input to the
31 PLL_SEL Input Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK. When LOW,
32 CLK_SEL Input Pulldown
selects XTAL_IN, XTAL _OUT. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C Input Capacitance 4 pF
IN
C Power Dissipation Capacitance (per output) V , V = 3.47V 25 pF
PD DDA DDO
R Input Pulldown Resistor 51 k
PULLDOWN
R Output Impedance 5 7 12
OUT
LOW SKEW, 1-TO-9 2 REVISION C 11/6/15
LVCMOS / LVTTL CLOCK MULTIPLIER