Low Skew, 1-to-12 LVCMOS / LVTTL 87973 Data Sheet Clock Multiplier/Zero Delay Buffer GENERAL DESCRIPTION FEATURES The 87973 is a LVCMOS/LVTTL clock generator. Fully integrated PLL The 87973 has three selectable inputs and provides Fourteen LVCMOS/LVTTL outputs twelve clock outputs, fourteen LVCMOS/LVTTL outputs. one feedback, one sync The 87973 is a highly exible device. The three selectable in- Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs puts (1 differential and 2 single ended inputs) are often used in CLK0, CLK1 can accept the following input levels: systems requiring redundant clock sources. Up to three LVCMOS or LVTTL different output frequencies can be generated among the three output banks. CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL The three output banks and feedback output each have their Output frequency range: 8.33MHz to 125MHz own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input VCO range: 200MHz to 480MHz frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) Output skew: 550ps (maximum) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. The input frequency Cycle-to-cycle jitter: 100ps (typical) range is 5MHz to 120MHz. Full 3.3V supply voltage The 87973 also has a QSYNC output which can by used for -40C to 85C ambient operating temperature system synchronization purposes. It monitors Bank A and Available in lead-free RoHS compliant package Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes Compatible with PowerPC and Pentium Microprocessors high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. PIN ASSIGNMENT Example Applications: 1. System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory mod- ule with zero delay. 2015 Integrated Device Technology, Inc 1 December 7, 201587973 Data Sheet BLOCK DIAGRAM VCO SEL PLL SEL REF SEL CLK 1 nCLK SYNC D Q QA0 0 FRZ CLK0 0 0 SYNC PHASE QA1 FRZ CLK1 VCO 1 1 DETECTOR SYNC LPF QA2 FRZ CLK SEL SYNC EXT FB QA3 FRZ D Q SYNC QB0 FRZ SYNC QB1 FRZ SYNC QB2 FRZ SYNC QB3 FRZ FSEL FB2 nMR/OE D Q QC0 POWER-ON SYNC 4, 6, 8, 12 RESET QC1 FRZ 4, 6, 8, 10 SYNC D Q QC2 FRZ 2, 4, 6, 8 SYNC QC3 FRZ 2 0 D Q 4, 6, 8, 10 FSEL A0:1 QFB 2 1 2 FSEL B0:1 SYNC PULSE 2 FSEL C0:1 SYNC SYNC D Q 3 QSYNC FSEL FB0:2 FRZFRZ DATA GENERATOR FRZ CLK OUTPUT DISABLE 12 CIRCUITRY FRZ DATA INV CLK 2015 Integrated Device Technology, Inc 2 December 7, 2015