2:1 LVDS Multiplexer With 1:2 Fanout 889474 and Internal Termination DATA SHEET GENERAL DESCRIPTION FEATURES The 889474 is a high speed 2-to-1 differential multiplexer Two differential LVDS outputs with integrated 2 output LVDS fanout buffer and internal INx, nINx pair can accept the following differential input levels: termination and is a member of the family of high performance LVPECL, LVDS, LVHSTL, CML clock solutions from IDT. The 889474 is optimized for 50 internal input termination to V high speed and very low output skew, making it suitable T for use in demanding applications such as SONET, Maximum output frequency: 2GHz (maximum) 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally Additive phase jitter, RMS: 0.06ps (typical) terminated differential input and VREF AC pins allow other differential signal families such as LVPECL, LVDS, LVHSTL and CML to be easily Output skew: 20ps (maximum) interfaced to the input with minimal use of external components. The Propagation delay: 700ps (maximum) 889474 is packaged in a small 4mm x 4mm 24-pin VFQFN package which makes it ideal for use in space-constrained applications. 2.5V operating supply -40C to 85C ambient operating temperature Available in lead-free RoHS-complaint package BLOCK DIAGRAM PIN ASSIGNMENT IN0 50 Q0 V 0 T0 24 23 22 21 20 19 50 nQ0 nIN0 VDD 1 18 GND V MUX nIN0 2 GND 17 REF AC0 IN1 VREF AC0 3 nc Q1 16 50 VT0 4 15 SEL V 1 nQ1 T1 50 IN0 5 14 GND nIN1 VDD 6 13 VDD V REF AC1 7 8 9 10 11 12 SEL 889474 24-Lead VFQFN 4mm x 4mm x 0.925mm package body K Package Top View 889474 REVISION A 11/11/15 1 2015 Integrated Device Technology, Inc. VDD Q0 nQ0 IN1 VDD VT1 VDD VREF AC1 nIN1 Q1 nQ1 VDD889474 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6, 9, 10, V Power Positive supply pins. DD 13, 19, 24 2, 20 nIN0, nIN1 Input Inverting differential clock inputs. 50 internal input termination to V . T 3, V REF AC0, Output Reference voltage for AC-coupled applications. 21 V REF AC1 4, 22 V V Input Termination inputs. T0, T1 5, 23 IN0, IN1 Input Non-inverting differential clock inputs. 50 internal input termination to V . T 7, 8 Q0, nQ0 Output Differential output pair. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair. LVDS interface levels. 14, 17, 18 GND Power Power supply ground. 15 SEL Input Pullup Input select pin. LVCMOS/LVTTL interface levels. 16 nc Unused No connect. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 25 k PULLUP TABLE 3. TRUTH TABLE Inputs Outputs IN0 nIN0 IN1 nIN1 SEL Q0:Q1 nQ0:nQ1 01 X X 0 0 1 10 X X 0 1 0 X X 011 0 1 X X 101 1 0 2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT 2 REVISION A 11/11/15 AND INTERNAL TERMINATION