8-Output Very Low Phase Jitter 8INT31H800A HCSL Fanout Buffer DATA SHEET General Description Features/Benefits The 8INT31H800A is an 8-output very high performance HCSL Extremely low additive phase jitter supports DB800H fanout buffer for High Performance Interconnect applications. It can requirements also be used at speeds up to 350MHz. There are four OE pins on the 3.3V operation standard industry power supply device, each controlling two outputs. Four OE pins each controlling two outputs easy control of clocks to CPU sockets Recommended Application Universal differential input can be driven by HCSL or LVPECL DB800H clock sources 1MHz to 350MHz operating frequency covers all popular Ethernet Output Features frequencies Eight HCSL differential pairs Space saving 32-pin 5x5mm VFQFN minimal board space Key Specifications Qx output-to-output skew within a pair: 22ps (typical) Qx output-to-output skew across all outputs: 32ps (typical) RMS additive phase jitter: 65fs (typical) Pin Assignment Block Diagram vOE 01 Q(0:1) vOE 23 31 30 29 28 27 26 25 32 Q(2:3) 1 24 Q0 Q4 2 nCLK IN nQ0 23 nQ4 CLK IN 3 22 Q1 Q5 Q(4:5) 4 21 nQ1 nQ5 vOE 45 8INT31H800A 5 Q2 20 Q6 6 Q(6:7) nQ2 19 nQ6 vOE 67 7 Q3 18 Q7 8 nQ3 17 nQ7 9 10 11 12 13 14 15 16 32-pin,5mmx5mmVFQFNPackage v prefix indicates internal 50k pull-down resistor 8INT31H800A REVISION 2 12/09/14 1 2014 Integrated Device Technology, Inc. V V DDO3.3 DDO3.3 vOE 67 GNDO CLK IN vOE 45 nCLK IN vOE 23 GND vOE 01 V IREF DD3.3 GNDO GNDO V V DDO3.3 DDO3.38INT31H800A DATA SHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Pin Name Type Pin Description 1 Q0 Output Non-inverting output of Differential Pair 0. 2 nQ0 Output Inverting output of Differential Pair 0. 3 Q1 Output Non-inverting output of Differential Pair 1. 4 nQ1 Output Inverting output of Differential Pair 1. 5 Q2 Output Non-inverting output of Differential Pair 2. 6 nQ2 Output Inverting output of Differential Pair 2. 7 Q3 Output Non-inverting output of Differential Pair 3. 8 nQ3 Output Inverting output of Differential Pair 3. 9V Power Power supply for outputs, nominal 3.3V. DDO3.3 Active Low input for enabling outputs 6 and 7. 10 vOE 67 Input Pulldown 0 = enable outputs, 1 = disable outputs 11 CLK IN Input True Input for differential reference clock. 12 nCLK IN Input Complementary Input for differential reference clock. 13 GND GND Ground pin. 14 V Power Power supply, nominal 3.3V. DD3.3 15 GNDO GND Ground pin for outputs. 16 V Power Power supply for outputs, nominal 3.3V. DDO3.3 17 nQ7 Output Inverting output of Differential Pair 7. 18 Q7 Output Non-inverting output of Differential Pair 7. 19 nQ6 Output Inverting output of Differential Pair 6. 20 Q6 Output Non-inverting output of Differential Pair 6. 21 nQ5 Output Inverting output of Differential Pair 5. 22 Q5 Output Non-inverting output of Differential Pair 5. 23 nQ4 Output Inverting output of Differential Pair 4. 24 Q4 Output Non-inverting output of Differential Pair 4. 25 V Power Power supply for outputs, nominal 3.3V. DDO3.3 26 GNDO GND Ground pin for outputs. This pin establishes the reference for the differential current-mode output pairs. It requires 27 IREF Output a fixed precision resistor to ground. 475 is the standard value for 100 differential impedance. Other impedances require different values. See data sheet. Active Low input for enabling outputs 0 and 1. 28 vOE 01 Input Pulldown 0 = enable outputs, 1 = disable outputs Active Low input for enabling outputs 2 and 3 29 vOE 23 Input Pulldown 0 = enable outputs, 1 = disable outputs Active Low input for enabling outputs 4 and 5. 30 vOE 45 Input Pulldown 0 = enable outputs, 1 = disable outputs 31 GNDO GND Ground pin for outputs. 32 V Power Power supply for outputs, nominal 3.3V. DDO3.3 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 2 REVISION 2 12/09/14