Low Skew, 2:1 LVPECL MUX with 1:6 8S58035I Fanout and Internal Termination Data Sheet General Description Features The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout Six LVPECL outputs Buffer. The 8S58035I is optimized for high speed and very low output INx, nINx inputs can accept the following differential input levels: skew, making it suitable for use in demanding applications such as LVPECL, LVDS, CML SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The internally terminated differential inputs and V pins allow other REF AC 50 internal input termination to V T differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external compo- Two selectable differential input pairs nents. The device also has a 2:1 MUX input, allowing for easy selec- Maximum output frequency: 3.2GHz tion between two clock reference sources. The 8S58035I is packaged in a small 5mm x 5mm 32-pin VFQFN package which Output Skew: 45ps (maximum) makes it ideal for use in space-constrained applications. Part-to-Part Skew: 200ps (maximum) Additive phase jitter, RMS: 47fs (typical), (f = 622.08MHz, 12kHz - 20MHz, V = 3.3V) REF CC Propagation Delay: 580ps (maximum) LVPECL mode operating voltage supply range: V = 2.5V5%, 3.3V10%, V = 0V CC EE -40C to 85C ambient operating temperature Block Diagram Pin Assignment Q0 32 31 302928 27 26 25 IN0 1 24 V EE nQ0 V 2 23 V T0 CC IN0 V 3 22 Q2 REF AC0 Q1 50 nIN0 4 21 nQ2 V 0 T0 nQ1 50 IN1 5 20 Q3 nIN0 V 6 19 nQ3 T1 Q2 V 7 18 V REF AC1 CC VREF AC0 nQ2 nIN1 8 17 V EE 9 10111213 14 15 16 IN1 50 Q3 1 V T1 50 nQ3 8S58035I nIN1 32-Lead VFQFN Q4 V REF AC1 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm Epad Size nQ4 Pullup K Package SEL Top View Q5 nQ5 2016 Integrated Device Technology, Inc 1 Revision A February 5, 2016 V V EE EE nc SEL V V CC CC nQ5 Q0 Q5 nQ0 nQ4 Q1 Q4 nQ1 V V CC CC8S58035I Data Sheet Table 1. Pin Descriptions Number Name Type Description Non-inverting differential LVPECL clock inputs. 1, 5 IN0, IN1 Input R = 50 termination to V T T. 2, 6 V , V Input Termination inputs. T0 T1 V , REF AC0 3, 7 Output Reference voltage for AC-coupled applications. V REF AC1 Inverting differential LVPECL clock inputs. 4, 8 Input nIN0, nIN1 R = 50 termination to V T T. 9, 17, 24, 32 V Power Negative supply pins. EE 10 nc No connect pin. 11, 16, 18, 23, V Power Positive supply pins. CC 25, 30 12, 13 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 14, 15 Output Differential output pair. LVPECL interface levels. nQ4, Q4 19, 20 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 21, 22 Output Differential output pair. LVPECL interface levels. nQ2, Q2 26, 27 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 28, 29 Output Differential output pair. LVPECL interface levels. nQ0, Q0 31 Input Pullup Input select pin. LVCMOS/LVTTL interface levels. SEL NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 51 k PULLUP Function Tables Table 3. SEL Function Table SEL Function 0 IN0, nIN0 input selected 1 IN, nIN1 input selected (default) 2016 Integrated Device Technology, Inc 2 Revision A February 5, 2016