VEE Low Skew, 2, 4, 8 Differential-to-LVPECL ICS8S73034I Clock Divider DATA SHEET General Description Features The ICS8S73034I is a high-speed, differential-to- LVPECL clock 2, 4 and 8 clock frequency divider divider designed for high-performance telecommunication, Three differential LVPECL output pairs computing and networking applications. High clock frequency One differential PCLK, nPCLK input pair capability and the differential design make the ICS8S73034I an ideal PCLK, nPCLK pair can accept the following differential input choice for performance clock distribution networks. The device levels: LVPECL, LVDS, CML frequency-divides the input clock by 2, 4 and 8. Each V bias voltage generator supports single-ended LVPECL clock frequency-divided clock signal is output at a separate LVPECL BB input signals output. The differential input pair can be driven by LVPECL, LVDS, CML and SSTL signals. Single-ended input signals are supported by LVCMOS control inputs using the integrated bias voltage generator (V ). The ICS8S73034I BB Maximum input frequency: 3.2GHz is optimized for 3.3V and 2.5V power supply voltages and the Translates any single-ended input signal to 3.3V LVPECL levels temperature range of -40 to +85C. The device is available in with bias resistors on nPCLK input space-saving 16-lead TSSOP and SOIC packages. LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown nEN D Q0 1 16 VCC Q0 2 nQ0 2 15 nEN Q VCC 3 nQ0 14 nc LE R 13 PCLK Q1 4 nQ1 12 nPCLK 5 Pulldown Q1 VCC 6 11 VBB PCLK 4 Pullup/Pulldown nPCLK Q2 7 10 MR nQ1 R nQ2 8 9 V BB ICS8S73034I Q2 8 nQ2 16-Lead SOIC, 150 Mil R 3.9mm x 9.9mm x 1.375mm package body Pulldown MR M Package Top View 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View ICS8S73034AMI REVISION A JUNE 8, 2011 1 2011 Integrated Device Technology, Inc.ICS8S73034I Data Sheet LOW SKEW , 2, 4, 8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 6, 16 V Power Power supply pins. CC 4, 5 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 7, 8 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 9V Power Negative supply pin. EE Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 10 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 11 V Output Bias voltage. BB 2 Pullup/ Inverting differential clock input. Defaults to / * V when left open. 3 CC 12 nPCLK Input Pulldown LVPECL interface levels. 13 PCLK Input Pulldown Non-inverting differential clock input. LVPECL interface levels. 14 nc Unused No connect. Synchronous clock enable. When logic LOW, the clock is enabled and 15 nEN Input Pulldown frequency-divided. When logic HIGH, the clock is disabled and the outputs remain stopped in the same logic state (hold). LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 75 k PULLDOWN R Input Pullup Resistor 37.5 k PULLUP Function Table Table 3. Truth Table Inputs PCLK nEN MR Function L L Divide H L Hold Q 0:2 X X H Reset Q 0:2 = Rising edge transition = Falling edge transition X = Dont care ICS8S73034AMI REVISION A JUNE 8, 2011 2 2011 Integrated Device Technology, Inc.