Low Skew, 1-to-4 Differential-to-LVDS 8S89832I Fanout Buffer Data Sheet Description Features The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout Four differential LVDS output pairs Buffer. The 8S89832I is optimized for high speed and very low output IN, nIN input pairs can accept the following differential input levels: skew, making it suitable for use in demanding applications such as LVPECL, LVDS, SSTL SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The 50 internal input termination to V T internally terminated differential input and VREF AC pin allow other Maximum output frequency: 2GHz differential signal families such as LVPECL, LVDS, and SSTL to be Output skew: 25ps (maximum) easily interfaced to the input with minimal use of external components. The device also has an output enable pin that may be Part-to-part skew: 200ps (maximum) useful for system test and debug purposes. Propagation delay: 550ps (maximum) The 8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN Additive phase jitter, RMS: 0.09ps (typical) package which makes it ideal for use in space-constrained Full 2.5V supply mode applications. -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Q0 16 15 14 13 Q1 1 12 IN nQ0 2 nQ1 11 VT 3 Q2 10 VREF AC IN Q1 50 nQ2 4 9 nIN V nQ1 T 5 6 7 8 50 nIN Q2 V REF AC 8S89832I nQ2 EN D Q 16-Lead VFQFN Q3 3mm x 3mm x 0.925mm package body CLK K Package nQ3 Top View 2017 Integrated Device Technology, Inc. 1 September 22, 2017 Q3 nQ0 nQ3 Q0 VDD VDD EN GND8S89832I Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2 Q1, nQ1 Output Differential output pair. LVDS interface levels. 3, 4 Q2, nQ2 Output Differential output pair. LVDS interface levels. 5, 6 Q3, nQ3 Output Differential output pair. LVDS interface levels. 7, 14 V Power Positive supply pins. DD Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is V /2V. Includes a DD 8 EN Input Pullup 37k pullup resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN. See Table 3A LVTTL / LVCMOS interface levels. 9 nIN Input Inverting differential clock input. 50 internal input termination to V . T 10 V Output Reference voltage for AC-coupled applications. REF AC 11 V Input Termination input. T 12 IN Input Non-inverting differential clock input. 50 internal input termination to V . T 13 GND Power Power supply ground. 15, 16 Q0, nQ0 Output Differential output pair. LVDS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 37 k PULLUP 2017 Integrated Device Technology, Inc. 2 September 22, 2017