Low Skew, 1-To-4 Differential-To-LVDS 8S89833 Datasheet Fanout Buffer w/Internal Termination Description Features The 8S89833 is a high speed 1-to-4 Differential-to-LVDS Fanout Four differential LVDS outputs Buffer with Internal Termination. The 8S89833 is optimized for high IN, nIN input pair can accept the following differential input levels: speed and very low output skew, making it suitable for use in LVPECL, LVDS, CML demanding applications such as SONET, 1 Gigabit and 10 Gigabit Output frequency: 2GHz Ethernet, and Fibre Channel. The internally terminated differential Cycle-to-cycle jitter, RMS: 3.5ps (maximum) input and VREF AC pin allow other differential signal families such as Additive phase jitter, RMS: 0.03ps (typical) LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components. The device also has an output Output skew: 30ps (maximum) enable pin which may be useful for system test and debug purposes. Part-to-part skew: 200ps (maximum) The 8S89833 is packaged in a small 3mm x 3mm 16-pin VFQFN Propagation Delay: 600ps (maximum) package which makes it ideal for use in space-constrained Full 3.3V supply mode applications. -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 nQ0 16 15 14 13 1 Q0 12 IN IN Q1 nQ0 2 11 VT 50 V nQ1 T Q1 3 10 VREF AC 50 nQ1 4 9 nIN nIN 5 6 7 8 Q2 V REF AC nQ2 Pullup EN DQ 8S89833 Q3 16-Lead VFQFN nQ3 3mm x 3mm x 0.925mm package body K Package Top View 2017 Integrated Device Technology, Inc. 1 September 22, 2017 Q2 nQ3 nQ2 Q3 VDD VDD EN GND8S89833 Datasheet Table 1. Pin Descriptions Number Name Type Description Differential output pair. Normally terminated with 100 across the pair. LVDS interface 1, 2 Q0, nQ0 Output levels. Differential output pair. Normally terminated with 100 across the pair. LVDS interface 3, 4 Q1, nQ1 Output levels. Differential output pair. Normally terminated with 100 across the pair. LVDS interface 5, 6 Q2, nQ2 Output levels. 7, 14 V Power Power supply pins. DD Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables 8 EN Input Pullup outputs. Internally connected to a 37k pullup resistor. LVTTL / LVCMOS interface levels. 9 nIN Input Inverting differential LVPECL clock input. RT = 50 termination to V . T Reference voltage for AC-coupled applications. Equal to V - 1.4V (approx.). Maximum DD 10 V Output REF AC sink/source current is 2mA. Input termination center-tap. Each side of the differential input pair terminates to a V pin. T 11 V Input T The V pins provide a center-tap to a termination network for maximum interface flexibility. T 12 IN Input Non-inverting differential clock input. RT = 50 termination to V . T 13 GND Power Power supply ground. Differential output pair. Normally terminated with 100 across the pair. LVDS interface 15, 16 Q3, nQ3 Output levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 37 k PULLUP 2017 Integrated Device Technology, Inc. 2 September 22, 2017