Differential-to-LVDS Buffer/Divider 8S89875I w/Internal Termination Datasheet Description Features The 8S89875I is a high speed Differential-to-LVDS Buffer/Divider Two LVDS output pairs w/Internal Termination. The 8S89875I has selectable 1, 2, 4, 8, Frequency divide select options: 1, 2, 4, 8, 16 16 output divider. The clock input has internal termination resistors, IN, nIN input can accept the following differential input levels: allowing it to interface with several differential signal types while LVPECL, LVDS, CML minimizing the number of required external components. Input frequency: 2.5GHz (maximum) The device is packaged in a small, 3mm x 3mm VFQFN package, Cycle-to-cycle jitter, RMS: 4.1ps (maximum) making it ideal for use on space-constrained boards. Total jitter: 18ps (maximum) Output skew: 15ps (maximum) Part-to-part skew: 280ps (maximum) Propagation delay: 1000ps (maximum) Full 2.5V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin compatible with the obsolete device, 889875AK Block Diagram Pin Assignment Pullup S2 16 15 14 13 1 Q0 12 IN nQ0 2 11 VT nRESET/ Enable Pullup Q1 3 10 nDISABLE VREF AC FF nQ1 4 9 nIN 5 6 7 8 Enable V REF AC MUX Q0 nQ0 MUX 8S89875I IN 16-Lead VFQFN Q1 50 2, 4, V T 3mm x 3mm x 0.9mm package body 8, 16 nQ1 50 K Package nIN Top View Pullup S1 Decoder Pullup S0 2018 Integrated Device Technology, Inc 1 January 11, 2018 S2 S0 nc S1 VDD VDD nRESET/ GND nDISABLE8S89875I Datasheet Table 1. Pin Descriptions Number Name Type Description Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be terminated 1, 2 Q0, nQ0 Output with 100 across the differential pair. LVDS interface levels. Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be terminated 3, 4 Q1, nQ1 Output with 100 across the differential pair. LVDS interface levels. Select pins. Internal 37k pullup resistor. Logic HIGH if left disconnected. Input 5, 15, 16 S2, S1, S0 Input Pullup threshold is V /2. LVCMOS/LVTTL interface levels. DD 6 nc Unused No connect. 7, 14 V Power Power supply pins. DD Synchronizing enable/disable pin. When LOW, resets the divider (divided by 2, 4, 8 or 16 mode) and sets the Qx outputs to a logic 0. When HIGH, the dividers and Qx nRESET/ 8 Input Pullup outputs are enabled. The reset and disable function occurs on the next high-to-low nDISABLE clock input transition. Input threshold is V /2V. Includes a 37k pull-up resistor. DD LVTTL / LVCMOS interface levels. 9 nIN Input Inverting differential LVPECL clock input. R = 50 termination to V . T T Reference voltage for AC-coupled applications. Equal to V 1.35V (approx.). DD 10 V Output REF AC Maximum sink/source current is 2mA. 11 V Input Termination center-tap input. T Non-inverting LVPECL differential clock input. 12 IN Input R = 50 termination to V . T T 13 GND Power Power supply ground. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 37 k PULLUP 2018 Integrated Device Technology, Inc 2 January 11, 2018