8SLVD1204-33NLGI Renesas

2:4, LVDS Output Fanout Buffer 8SLVD1204-33 DATASHEET Description Features The 8SLVD1204-33 is a high-performance differential LVDS fanout Four low skew, low additive jitter LVDS output pairs buffer. The device is designed for the fanout of high-frequency, very Two selectable differential clock input pairs low additive phase-noise clock and data signals. The 8SLVD1204-33 Differential PCLKx, nPCLKx pairs can accept the following is characterized to operate from a 3.3V power supply. Guaranteed differential input levels: LVDS, LVPECL output-to-output and part-to-part skew characteristics make the Maximum input clock frequency: 2GHz 8SLVD1204-33 ideal for those clock distribution applications LVCMOS/LVTTL interface levels for the control input select pin demanding well-defined performance and repeatability. Output skew: 20ps (maximum) Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy Propagation delay: 310ps (maximum) interfacing of single-ended signals to the device inputs. The device is Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP optimized for low power consumption and low additive phase noise. 10kHz - 20MHz: 100fs (maximum) Full 3.3V supply voltage Lead-free (RoHS 6), 16-Lead VFQFPN packaging -40C to 85C ambient operating temperature Block Diagram Pin Assignment VDD 12 11 10 9 Q0 Pulldown 13 8 Q2 V REF PCLK0 Pullup/Pulldown nQ0 nPCLK0 14 7 nPCLK0 nQ2 8SLVD1204-33 Q1 6 15 PCLK0 GND GND Q3 0 8XXXXXX VDD nQ1 5 16 V nQ3 DD 1 2 34 Pulldown Q2 PCLK1 1 Pullup/Pulldown nPCLK1 nQ2 GND GND Q3 16-pin, 3 x 3 mm VFQFPN Package VDD nQ3 Pullup/Pulldown SEL GND Reference Voltage VREF Generator 8SLVD1204-33 November 29, 2018 1 2018 Integrated Device Technology, Inc. GND nQ1 SEL Q1 PCLK1 nQ0 nPCLK1 Q08SLVD1204-33 DATASHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. Pullup/ Reference select control pin. See Table 3 for function. LVCMOS/LVTTL 2 SEL Input Pulldown interface levels. 3 PCLK1 Input Pulldown Non-inverting differential clock/data input. Pullup/ 4 nPCLK1 Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 5V Power Power supply pin. DD 6 PCLK0 Input Pulldown Non-inverting differential clock/data input. Pullup/ 7 nPCLK0 Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 8V Output Bias voltage reference for the PCLKx, nPCLKx inputs. REF 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN Input Pullup Resistor 51 k R PULLUP Function Table Table 3. SEL Input Selection Function Table Input SEL Operation 0 PCLK0, nPCLK0 is the selected differential clock input. 1 PCLK1, nPCLK1 is the selected differential clock input. /2. Internally set to V DD Open (default) Input buffers are disabled and outputs are static. NOTE: SEL is an asynchronous control. 8SLVD1204-33 November 29, 2018 2 2018 Integrated Device Technology, Inc.