2:4, LVDS Output Fanout Buffer, 2.5V 8S L VD1204 Dat ash eet Description Features The 8SLVD1204 is a high-performance differential LVDS fanout Four low skew, low additive jitter LVDS output pairs buffer. The device is designed for the fanout of high-frequency, very Two selectable differential clock input pairs low additive phase-noise clock and data signals. The 8SLVD1204 is Differential PCLK, nPCLK pairs can accept the following characterized to operate from a 2.5V power supply. Guaranteed differential input levels: LVDS, LVPECL output-to-output and part-to-part skew characteristics make the 8SLVD1204 ideal for those clock distribution applications demanding Maximum input clock frequency: 2GHz well-defined performance and repeatability. LVCMOS/LVTTL interface levels for the control input select pin Two selectable differential inputs and four low skew outputs are Output skew: 20ps (maximum) available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is Propagation delay: 300ps (maximum) optimized for low power consumption and low additive phase noise. Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP 10kHz - 20MHz: 95fs (maximum) Full 2.5V supply voltage Lead-free (RoHS 6), 16-Lead VFQFPN packaging Supports case temperature 105C operations -40C to 85C ambient operating temperature Block Diagram Pin Assignment VDD 12 11 10 9 Pulldown Q2 VREF PCLK0 13 8 Q0 Pullup/Pulldown 14 nPCLK0 nQ2 7 nPCLK0 nQ0 Q3 15 6 PCLK0 nQ3 16 5 VDD 1 2 3 4 GND GND Q1 0 VDD nQ1 8SLVD1204 Pulldown Q2 PCLK1 16 lead VFQFPN Pullup/Pulldown 1 nPCLK1 nQ2 3.0mm x 3.0mm x 0.9mm package body 1.7mm x 1.7mm ePad NL Package GND GND Q3 Top View VDD nQ3 Pullup/Pulldown SEL GND Reference V Voltage REF Generator May 11, 2021 R31DS0031EU0600 1 2021 Renesas Electronics Corporation GND nQ1 SEL Q1 PCLK1 nQ0 nPCLK1 Q08SLVD1204 DATASHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. Pullup/ Reference select control pin. See Table 3 for function. LVCMOS/LVTTL 2 SEL Input Pulldown interface levels. 3 PCLK1 Input Pulldown Non-inverting differential clock/data input. Pullup/ 4 nPCLK1 Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 5 V Power Power supply pin. DD 6 PCLK0 Input Pulldown Non-inverting differential clock/data input. Pullup/ 7 nPCLK0 Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 8 V Output Bias voltage reference for the PCLK, nPCLK inputs. REF 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Function Table Table 3. SEL Input Selection Function Table Input SEL Operation 0 PCLK0, nPCLK0 is the selected differential clock input. 1 PCLK1, nPCLK1 is the selected differential clock input. Open (default) Input buffers are disabled and outputs are static. NOTE: SEL is an asynchronous control. May 11, 2021 R31DS0031EU0600 2 2021 Renesas Electronics Corporation