8SLVD2102NLGI/W Renesas

Dual 1:2, LVDS Output Fanout Buffer 8SLVD2102 Datasheet Description Features The 8SLVD2102 is a high-performance differential dual 1:2 LVDS Two 1:2, low skew, low additive jitter LVDS fanout buffers fanout buffer. The device is designed for the fanout of high-frequency, Two differential clock inputs very low additive phase-noise clock and data signals. The Differential pairs can accept the following differential input 8SLVD2102 is characterized to operate from a 2.5V power supply. levels: LVDS and LVPECL Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2102 ideal for those clock distribution applications Maximum input clock frequency: 2GHz demanding well-defined performance and repeatability. Output bank skew: 15ps (maximum) Two independent buffers with two low skew outputs each are Propagation delay: 300ps (maximum) available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is Low additive phase jitter: 200fs, RMS (maximum) optimized for low power consumption and low additive phase noise. f = 156.25MHz, V = 1V, V = 1V, REF PP CMR Integration Range 10kHz - 20MHz 2.5V supply voltage Maximum device current consumption (I ): 90mA DD Lead-free (RoHS 6) 16-Lead VFQFPN package -40C to 85C ambient operating temperature Block Diagram Pin Assignment V DD QA0 nQA0 PCLKA 16 15 14 13 1 12 nQA1 GND nPCLKA QA1 nQA1 11 2 QA1 EN 8SLVD2102I 10 nQA0 3 PCLKB 8XXXXXX V DD QB0 nQB0 9 QA0 4 PCLKB nPCLKB 5 6 78 nPCLKB QB1 nQB1 Voltage V REF Reference 1616-pin,-pin, 33.0mm.0 x 3.0x m3.0mmm VFQFPNVFQFN PPacackagekage V DD EN 8SLVD2102 January 21, 2018 1 2018 Integrated Device Technology, Inc. V nQB1 DD PCLKA QB1 nPCLKA nQB0 V REF QB08SLVD2102 DATASHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. Pullup/ 2 EN Input Output enable pin. Pulldown 3 PCLKB Input Pulldown Non-inverting differential clock/data input. Pullup/ 4 nPCLKB Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 5V Power Power supply pin. DD 6 PCLKA Input Pulldown Non-inverting differential clock/data input. Pullup/ 7 nPCLKA Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown Output Bias voltage reference for the PCLKx, nPCLKx inputs. 8V REF 9, 10 QA0, nQA0 Output Differential output pair. LVDS interface levels. 11, 12 QA1, nQA1 Output Differential output pair. LVDS interface levels. 13, 14 QB0, nQB0 Output Differential output pair. LVDS interface levels. 15, 16 QB1, nQB1 Output Differential output pair. LVDS interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2pF C IN Input Pulldown R PCLK inputs 51 k PULLDOWN Resistor Input Pullup R PCLK inputs 51 k PULLUP Resistor Input Pulldown R EN input 51 k PULLDOWN Resistor Input Pullup R EN input 51 k PULLUP Resistor Table 3. EN Input Selection Function Table Input EN Operation 0 (Low) Outputs are disabled and outputs are static at Qx = 0 (low level) and nQx = 1 (high level). Bank A outputs are enabled and Bank B outputs are disabled at the following static levels: QBx = 0 (low level) and 1 (High) nQBx = 1 (high level). Open All outputs enabled. NOTE: EN is an asynchronous control. 8SLVD2102 January 21, 2018 2 2018 Integrated Device Technology, Inc.