8SLVP1104ANLGI Renesas

Low Phase Noise, 1-to-4, 3.3V, 2.5V IDT8SLVP1104I LVPECL Output Fanout Buffer DATASHEET Description Features The IDT8SLVP1104I is a high-performance differential LVPECL Four low skew, low additive jitter LVPECL differential output pairs fanout buffer. The device is designed for the fanout of high-frequency, Differential LVPECL input pair can accept the following differential very low additive phase-noise clock and data signals. The input levels: LVDS, LVPECL, CML IDT8SLVP1104I is characterized to operate from a 3.3V or 2.5V Differential PCLKx pairs can also accept single-ended LVCMOS power supply. levels. See the Applications section Writing the Differential Input Guaranteed output-to-output and part-to-part skew characteristics Levels to Accept Single-ended Levels (Figures 1 and 2) make the IDT8SLVP1104I ideal for those clock distribution Maximum input clock frequency: 2GHz applications demanding well-defined performance and LVCMOS interface levels for the control input (input select) repeatability.Four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to Output skew: 5ps (typical) the device inputs. The device is optimized for low power consumption Propagation delay: 320ps (maximum) and low additive phase noise. Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP 12kHz - 20MHz: 40fs (maximum) Maximum device current consumption (I ): 60mA (maximum) EE Full 3.3V or 2.5V supply voltage Lead-free (RoHS 6) packaging -40C to 85C ambient operating temperature Block Diagram Pin Assignment V CC 12 11 10 9 Pulldown Q0 Q2 13 8 VREF PCLK Pullup/Pulldown nQ0 nQ2 14 7 nPCLK nPCLK Q3 15 6 PCLK Q1 nQ3 16 5 VCC nQ1 f 1 2 3 4 REF Q2 nQ2 IDT8SLVP1104I Q3 16 lead VFQFPN nQ3 3.0mm x 3.0mm x 0.925mm package body 1.7mm x 1.7mm Epad Size NL Package Top View Voltage V REF Reference IDT8SLVP1104ANLGI MARCH 13, 2018 1 2018 Integrated Device Technology, Inc. VEE nQ1 nc Q1 nc nQ0 nc Q0IDT8SLVP1104I Datasheet LOW PHASE NOISE, 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1V Power Negative supply pin. EE 2 nc Unused Do not connect. 3 nc Unused Do not connect. 4 nc Unused Do not connect. 5V Power Power supply pin. CC 6 PCLK Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ /2 default when left Inverting differential LVPECL clock/data input. V CC 7nPCLK Input Pulldown floating. 8V Output Bias voltage reference for the PCLK inputs. REF 9, 10 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVPECL interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2 pF C IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP IDT8SLVP1104ANLGI MARCH 13, 2018 2 2018 Integrated Device Technology, Inc.