Low Phase Noise, 2:4, 3.3V, 2.5V 8S LV P1204 LVPECL Output Fanout Buffer D ATA S HE E T Description Features The 8SLVP1204 is a high-performance differential LVPECL fanout Four low skew, low additive jitter LVPECL output pairs buffer. The device is designed for the fanout of high-frequency, very Two selectable, differential clock input pairs low additive phase-noise clock and data signals. The 8SLVP1204 is Differential PCLKx pairs can accept the following differential input characterized to operate from a 3.3V or 2.5V power supply. levels: LVDS, LVPECL, CML Guaranteed output-to-output and part-to-part skew characteristics Differential PCLKx pairs can also accept single-ended LVCMOS make the 8SLVP1204 ideal for clock distribution applications that levels. See Applications Information, Wiring the Differential Input demand well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The to Accept Single-Ended Levels (Figures 1A and 1B) integrated bias voltage reference enables easy interfacing of Maximum input clock frequency: 2GHz single-ended signals to the device inputs. The device is optimized for LVCMOS interface levels for the control input, (input select) low power consumption and low additive phase noise. Output skew: 5ps (typical), at 3.63V Propagation delay: 200ps (typical), at 3.63V Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP 12kHz - 20MHz: 40fs (maximum), at 3.63V Maximum device current consumption (I ): 60mA (maximum), EE at 3.63V Full 3.3V5%, 3.3V10% or 2.5V5% supply Lead-free (RoHS 6), 16-Lead VFQFPN packaging -40C to 85C ambient operating temperature Supports case temperature 105C operations Supports PCI Express Gen15 Block Diagram Pin Assignment V CC 16 15 14 13 1 VEE 12 nQ1 Pulldown Q0 PCLK0 Pullup/Pulldown nQ0 SEL 2 11 Q1 nPCLK0 3 PCLK1 10 nQ0 Q1 nQ1 0 f REF nPCLK1 4 Q0 9 5 6 7 8 1 Q2 V CC nQ2 Pulldown PCLK1 Q3 Pullup/Pulldown nPCLK1 nQ3 8SLVP1204 16-Lead, 3mm x 3mm VFQFPN Package Pulldown SEL Voltage V REF Reference R31DS0034EU1100 MAY 20, 2021 1 2021 Renesas Electronics Corporation VCC nQ3 PCLK0 Q3 nPCLK0 nQ2 VREF Q28SLVP1204 DATASHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 V Power Negative supply pin. EE Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface 2 SEL Input Pulldown levels. 3 PCLK1 Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ 4 nPCLK1 Input Inverting differential LVPECL clock/data input. V /2 default when left floating. CC Pulldown 5 V Power Power supply pins. CC 6 PCLK0 Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ 7 nPCLK0 Input Inverting differential LVPECL clock/data input. V /2 default when left floating. CC Pulldown 8 V Output Bias voltage reference for the PCLK inputs. REF 9, 10 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVPECL interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Function Table Table 3. SEL Input Selection Function Table Input SEL Operation 0 (default) PCLK0, nPCLK0 is the selected differential clock input. 1 PCLK1, nPCLK1 is the selected differential clock input. NOTE: SEL is an asynchronous control. R31DS0034EU1100 MAY 20, 2021 2 2021 Renesas Electronics Corporation