Low Phase Noise, 1-to-8, 3.3V, 2.5V 8S LV P1208 LVPECL Output Fanout Buffer Da t as he et General Description Features The 8SLVP1208 is a high-performance differential LVPECL fanout Eight low skew, low additive jitter LVPECL output pairs buffer. The device is designed for the fanout of high-frequency, very Two selectable, differential clock input pairs low additive phase-noise clock and data signals. The 8SLVP1208 is Differential pairs can accept the following differential input characterized to operate from a 3.3V and 2.5V power supply. levels: LVDS, LVPECL, CML Guaranteed output-to-output and part-to-part skew characteristics Maximum input clock frequency: 2GHz make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two LVCMOS interface levels for the control input (input select) selectable differential inputs and eight low skew outputs are Output skew: 28ps (typical) available. The integrated bias voltage generators enables easy Propagation delay: 410ps (maximum) interfacing of single-ended signals to the device inputs. The device is Low additive phase jitter, RMS: 54.1fs (maximum) optimized for low power consumption and low additive phase noise. (f = 156.25MHz, V = 1V, 12kHz20MHz) REF PP Full 3.3V and 2.5V supply voltage Maximum device current consumption (I ): 141mA EE Available in lead-free (RoHS 6), 28-Lead VFQFPN package -40C to 85C ambient operating temperature Supports case temperature 105C operations Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also accept single-ended LVCMOS levels. See Applications section Wiring the Differential Input to Accept Single-Ended Levels (Figure 1A and Figure 1B) Supports PCI Express Gen15 Block Diagram Pin Assignment Q0 V CC nQ0 Pulldown PCLK0 Q1 Pullup/Pulldown nQ1 nPCLK0 Q2 0 nQ2 f REF Q3 V 1 CC nQ3 Pulldown PCLK1 Q4 Pullup/Pulldown nQ4 nPCLK1 Q5 nQ5 Pulldown Q6 8SLVP1208 SEL nQ6 28-VFQFPN Voltage V REF Reference Q7 Top View nQ7 R31DS0035EU0800 May 20, 2021 1 2021 Renesas Electronics Corporation8SLVP1208 DATASHEET Pin Descriptions and Characteristics 1 Table 1. Pin Descriptions Number Name Type Description 1, 14 V Power Negative supply pins. EE 2, 3 Q7, nQ7 Output Differential output pair. 7 LVPECL interface levels. Reference select control. See Table 3 for function. LVCMOS/LVTTL 4 SEL Input Pulldown interface levels. 5 PCLK1 Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ Inverting differential LVPECL clock/data input. V /2 default when left CC 6 nPCLK1 Input Pulldown floating. 7 V Output Bias voltage reference for the nPCLK inputs. REF 8, 15, 28 V Power Power supply pins. CC 9 PCLK0 Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ Inverting differential LVPECL clock/data input. V /2 default when left CC 10 nPCLK0 Input Pulldown floating. 11 nc Unused Do not connect. 12, 13 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 16, 17 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. 18, 19 Q2, nQ2 Output Differential output pair 2. LVPECL interface levels. 20, 21 Q3, nQ3 Output Differential output pair 3. LVPECL interface levels. 22, 23 Q4, nQ4 Output Differential output pair 4. LVPECL interface levels. 24, 25 Q5, nQ5 Output Differential output pair 5. LVPECL interface levels. 26, 27 Q6, nQ6 Output Differential output pair 6. LVPECL interface levels. NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Function Table 1 Table 3. SEL Input Selection Function Table Input SEL Operation 0 (default) PCLK0, nPCLK0 is the selected differential clock input 1 PCLK1, nPCLK1 is the selected differential clock input NOTE 1: SEL is an asynchronous control. R31DS0035EU0800 May 20, 2021 2 2021 Renesas Electronics Corporation