Low Phase Noise, 1-to-12, 3.3V, 2.5V 8SL VP 1212 LVPECL Output Fanout Buffer DA TAS H E E T Description Features The 8SLVP1212 is a high-performance, 12 output differential Twelve low skew, low additive jitter LVPECL outputs LVPECL fanout buffer. The device is designed for the fanout of Two selectable, differential clock inputs high-frequency, very low additive phase-noise clock and data signals. Differential pairs can accept the following differential input The 8SLVP1212 is characterized to operate from a 3.3V and 2.5V levels: LVDS, LVPECL, CML power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1212 ideal for those clock distribution Maximum input clock frequency: 2GHz applications demanding well-defined performance and repeatability. LVCMOS interface levels for the control input (input select) Two selectable differential inputs and twelve low skew outputs are Output skew: 33ps (maximum) available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is Propagation delay: 550ps (maximum) optimized for low power consumption and low additive phase noise. Low additive phase jitter, RMS at f = 156.25MHz, V = 1V, REF PP 12kHz20MHz: 60fs (maximum) Full 3.3V and 2.5V supply voltage Device current consumption (I ): 131mA (maximum) EE Available in Lead-free (RoHS 6), 40-VFQFPN package -40C to +85C ambient operating temperature Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also accept single-ended LVCMOS levels. See Applications section Block Diagram Wiring the Differential Input Levels to Accept Single-ended Levels (Figure 1A and Figure 1B) Q0 nQ0 Supports PCI Express Gen15 Q1 nQ1 Pin Assignment Q2 nQ2 V CC Q3 nQ3 30 29 28 27 26 25 24 23 22 21 PCLK0 V 31 20 V CC CC Q4 nPCLK0 Q8 32 19 nQ3 nQ4 nQ8 33 18 Q3 Q5 Q9 34 17 nQ2 f nQ5 REF nQ9 35 16 Q2 Q10 36 15 nQ1 V Q6 CC nQ10 37 14 Q1 nQ6 Q11 38 13 nQ0 PCLK1 Q7 nQ11 39 12 Q0 nQ7 nPCLK1 V 40 11 V CC CC 1 2 3 4 5 6 7 8 9 10 Q8 nQ8 Q9 SEL nQ9 Q10 8SLVP1212 nQ10 Voltage V 40-VFQFPN REF Reference Q11 6 x 6 x 0.9 mm package body, nQ11 Top View R31DS0036EU0300 MAY 20, 2021 1 2021 Renesas Electronics Corporation SEL V EE PCLK1 nQ7 nPCLK1 Q7 nc nQ6 V CC Q6 V nQ5 CC VREF Q5 nPCLK0 nQ4 PCLK0 Q4 V nc EE8SLVP1212 Datasheet Table 1. Pin Descriptions Number Name Type Description Reference select control. See Table 3A for function. 1 SEL Input Pulldown LVCMOS/LVTTL interface levels. 2 PCLK1 Input Pulldown Non-inverting LVPECL differential clock/data input. 3 nPCLK1 Input Pulldown/Pullup Inverting LVPECL differential clock/data input. 4, 10 nc Unused Do not connect. 5, 6, 11, 20, V Power Power supply pins. CC 31, 40 7 V Output Bias voltage reference. REF 8 nPCLK0 Input Pulldown/Pullup Inverting LVPECL differential clock/data input. 9 PCLK0 Input Pulldown Non-inverting LVPECL differential clock/data input. 12, 13 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 14, 15 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. 16, 17 Q2, nQ2 Output Differential output pair 2. LVPECL interface levels. 18, 19 Q3, nQ3 Output Differential output pair 3. LVPECL interface levels. 21, 30 V Power Negative power supply pins. EE 22, 23 Q4, nQ4 Output Differential output pair 4. LVPECL interface levels. 24, 25 Q5, nQ5 Output Differential output pair 5. LVPECL interface levels. 26, 27 Q6, nQ6 Output Differential output pair 6. LVPECL interface levels. 28, 29 Q7, nQ7 Output Differential output pair 7. LVPECL interface levels. 32, 33 Q8, nQ8 Output Differential output pair 8. LVPECL interface levels. 34, 35 Q9, nQ9 Output Differential output pair 9. LVPECL interface levels. 36, 37 Q10, nQ10 Output Differential output pair 10. LVPECL interface levels. 38, 39 Q11, nQ11 Output Differential output pair 11. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Function Table Table 3. SEL Input Section Function Table Input SEL Operation 0 (default) PCLK0, nPCLK0 is the selected differential clock input 1 PCLK1, nPCLK1 is the selected differential clock input NOTE: SEL is an asynchronous control. R31DS0036EU0300 MAY 20, 2021 2 2021 Renesas Electronics Corporation