Low Phase Noise, Dual 1-to-2, 3.3V, 8SLVP2102 2.5V LVPECL Output Fanout Buffer Datasheet Description Features The 8SLVP2102 is a high-performance differential LVPECL fanout Two low skew, low additive jitter LVPECL output pairs buffer. The device is designed for the fanout of high-frequency, very Two selectable, differential clock input pairs low additive phase-noise clock and data signals. The 8SLVP2102 is Differential pairs can accept the following differential input characterized to operate from a 3.3V or 2.5V power supply. levels: LVDS, LVPECL, CML Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP2102 ideal for those clock distribution applications Maximum input clock frequency: 2GHz demanding well-defined performance and repeatability. Output skew: 5ps (typical) Two selectable differential inputs and four low skew outputs are Propagation delay: 225ps (maximum) available. The integrated bias voltage reference enables easy Low additive phase jitter, RMS, f = 156.25MHz, V = 1V, REF PP interfacing of single-ended signals to the device inputs. The device is 12kHz 20MHz: 36fs (maximum) optimized for low power consumption and low additive phase noise. Full 3.3V and 2.5V supply voltage Maximum device current consumption (I ): 56mA (maximum) EE Available in lead-free (RoHS 6), 16-Lead VFQFPN package -40C to 85C ambient operating temperature Supports case temperature 105C operations Accepts single-ended LVCMOS levels. See Applications section Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also accept single-ended LVCMOS levels. See Applications section Wiring the Differential Input Levels to Accept Single-ended Levels (Figure 1A and Figure 1B) Pin Assignment Block Diagram V CC 12 11 10 9 QA0 13 8 VREF QB0 nQA0 14 7 nPCLKA nQB0 PCLKA 15 6 PCLKA nPCLKA QB1 QA1 16 nQB1 5 VCC nQA1 1 2 3 4 V CC QB0 nQB0 8SLVP2102 PCLKB nPCLKB 16-Lead VFQFPN QB1 3.0mm x 3.0mm x 0.925mm package body nQB1 NL Package Top View Voltage V REF Reference 2018 Integrated Device Technology, Inc. 1 March 13, 2018 VEE nQA1 nc QA1 PCLKB nQA0 nPCLKB QA08SLVP2102 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description Power 1V Negative supply pin. EE 2 nc Unused Do not connect. 3 PCLKB Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ /2 default when left Inverting differential LVPECL clock/data input. V CC 4 nPCLKB Input Pulldown floating. 5V Power Power supply pins. CC 6 PCLKA Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ /2 default when left Inverting differential LVPECL clock/data input. V CC 7 nPCLKA Input Pulldown floating. Output Bias voltage reference for the PCLK, nPCLK inputs. 8V REF 9, 10 QA0, nQA0 Output Differential output pair A0. LVPECL interface levels. 11, 12 QA1, nQA1 Output Differential output pair A1. LVPECL interface levels. 13, 14 QB0, nQB0 Output Differential output pair B0. LVPECL interface levels. 15, 16 QB1, nQB1 Output Differential output pair B1. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2 pF C IN Input Pulldown Resistor 51 k R PULLDOWN Input Pullup Resistor 51 k R PULLUP 2018 Integrated Device Technology, Inc. 2 March 13, 2018