Low Phase Noise, Dual 1-to-8, 3.3V, 8SLVP2108 2.5V LVPECL Output Fanout Buffer Datasheet Description Features The 8SLVP2108 is a high-performance differential dual 1:8 Two 1:8, low skew, low additive jitter LVPECL fanout buffers LVPECL fanout buffer. The device is designed for the fanout of Two differential clock inputs high-frequency, very low additive phase-noise clock and data Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can signals. accept the following differential input levels: LVDS, LVPECL, The 8SLVP2108 is characterized to operate from a 3.3V or 2.5V CML power supply. Guaranteed output-to-output and part-to-part skew Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can characteristics make the 8SLVP2108 ideal for those clock also accept single-ended LVCMOS levels. See Applications distribution applications demanding well-defined performance and section Wiring the Differential Input Levels to Accept repeatability. Two independent buffers with eight low skew outputs Single-ended Levels (Figure 1A and Figure 1B). each are available. The integrated bias voltage references enable Maximum input clock frequency: 2GHz easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive Output bank skew: 15ps (typical) phase noise. Propagation delay: 390ps (maximum) Low additive phase jitter, RMS: 54fs (maximum) (f = 156.25MHz, V = 1V, 12kHz 20MHz, V = 3.3V) REF PP CC Full 3.3V and 2.5V supply voltage Maximum device current consumption (I ): 143mA EE Available in Lead-free (RoHS 6), 48-Lead VFQFN package Block Diagram Supports case temperature 105C operations -40C to 85C ambient operating temperature QA0 nQA0 QA1 nQA1 V CC QA2 nQA2 PCLKA Pin Assignments nPCLKA 36 35 34 33 32 31 30 29 28 27 26 25 V 37 24 V CC CC QB3 38 23 nQA4 Voltage V QA7 REFA Reference 39 QA4 nQB3 22 nQA7 QB4 40 8SLVP2108 21 nQA3 nQB4 41 20 QA3 48-lead VFQFN QB0 42 19 nQA2 QB5 nQB0 7mm x 7mm x 0.8mm nQB5 43 18 QA2 package body QB6 44 17 nQA1 QB1 NL Package nQB6 45 16 QA1 nQB1 Top View 46 QB7 15 nQA0 V CC QB2 47 14 QA0 nQB7 V 48 CC 13 V nQB2 CC PCLKB 1 2 3 4 5 6 7 8 9 10 11 12 nPCLKB Voltage V REFB QB7 Reference nQB7 2019 Integrated Device Technology, Inc. 1 January 15, 2019 VEE nQB2 QB2 nc PCLKB nQB1 QB1 nPCLKB nQB0 VREFB QB0 VCC nQA7 VCC QA7 VREFA nQA6 nPCLKA QA6 PCLKA nQA5 nc VEE QA58SLVP2108 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 12 V Power Negative supply pins. EE 2, 11 nc Unused Do not connect. 3 PCLKB Input Pulldown Non-inverting LVPECL differential clock/data input. Pullup/ 4 nPCLKB Input Inverting LVPECL differential clock input. Pulldown 5V Output Bias voltage reference for the PCLKB, nPCLKB input pair. REFB 6, 7, 13, V Power Power supply pins. CC 24, 37, 48 8V Output Bias voltage reference for the PCLKA, nPCLKA input pair. REFA Pullup/ 9 nPCLKA Input Inverting LVPECL differential clock input. Pulldown 10 PCLKA Input Pulldown Non-inverting LVPECL differential clock/data input. 14, 15 QA0, nQA0 Output Differential output pair A0. LVPECL interface levels. 16, 17 QA1, nQA1 Output Differential output pair A1. LVPECL interface levels. 18, 19 QA2, nQA2 Output Differential output pair A2. LVPECL interface levels. 20, 21 QA3, nQA3 Output Differential output pair A3. LVPECL interface levels. 22, 23 QA4, nQA4 Output Differential output pair A4. LVPECL interface levels. 25, 26 QA5, nQA5 Output Differential output pair A5. LVPECL interface levels. 27, 28 QA6, nQA6 Output Differential output pair A6. LVPECL interface levels. 29, 30 QA7, nQA7 Output Differential output pair A7. LVPECL interface levels. 31, 32 QB0, nQB0 Output Differential output pair B0. LVPECL interface levels. 33, 34 QB1, nQB1 Output Differential output pair B1. LVPECL interface levels. 35, 36 QB2, nQB2 Output Differential output pair B2. LVPECL interface levels. 38, 39 QB3, nQB3 Output Differential output pair B3. LVPECL interface levels. 40, 41 QB4, nQB4 Output Differential output pair B4. LVPECL interface levels. 42, 43 QB5, nQB5 Output Differential output pair B5. LVPECL interface levels. 44, 45 QB6, nQB6 Output Differential output pair B6. LVPECL interface levels. 46, 47 QB7, nQB7 Output Differential output pair B7. LVPECL interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN Input Pullup Resistor 51 k R PULLUP 2019 Integrated Device Technology, Inc. 2 January 15, 2019