Low Voltage 1:20 Differential 8T 33F S6221 PECL/HSTL Clock Fanout Buffer D ATA S HE E T Description Features The 8T33FS6221 is a bipolar monolithic differential clock fanout 1:20 differential clock fanout buffer buffer. Designed for most demanding clock distribution systems, the 50ps typical device skew 8T33FS6221 supports various applications that require the SiGe technology distribution of precisely aligned differential clock signals. Using SiGe Maximum output frequency: 2GHz technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target PECL compatible differential clock outputs applications for this clock driver is high performance clock PECL/ HSTL compatible differential clock inputs distribution in computing, networking and telecommunication Single 3.3V or 2.5V supply systems. Standard 52 lead LQFP package with exposed pad for enhanced The 8T33FS6221 is designed for low skew clock distribution thermal characteristics systems and supports clock frequencies up to 2GHz. The device accepts two clock sources. The CLK0 input can be driven by PECL Supports industrial temperature range compatible signals, the CLK1 input accepts HSTL compatible Lead-free Packaging signals. The selected input signal is distributed to 20 identical, differential PECL outputs. If V is connected to the nCLK0 or BB nCLK1 input and bypassed to GND by a 10nF capacitor, the 8T33FS6221 can be driven by single-ended PECL signals utilizing the V bias voltage output. BB In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. Pin Assignment The 8T33FS6221 can be operated from a single 3.3V or 2.5V supply. Block Diagram 39 38 37 36 35 34 33 32 31 30 29 28 27 Q0 40 nQ0 V 26 Q12 CC Q1 41 nQ5 25 nQ12 nQ1 V CC 42 Q5 24 Q13 Q2 Pulldown nQ2 CLK0 nQ4 43 23 nQ13 Pullup/Pulldown Q3 nCLK0 nQ3 Q4 44 22 Q14 45 nQ3 21 nQ14 0 V EE 46 8T33FS6221 Q3 20 Q15 1 47 nQ2 19 nQ15 V CC 48 18 Q16 Q2 Pulldown CLK1 Q16 Pullup/Pulldown nCLK1 nQ16 49 nQ1 17 nQ16 Q17 50 Q1 16 Q17 nQ17 V 51 nQ0 15 nQ17 EE Q18 nQ18 52 Q0 14 V CC Q19 Pulldown 123456789 10111213 nQ19 CLK SEL V BB V EE 52-pin,10mmx10mmLQFPPackage,exposedpad 8T33FS6221 R31DS0008EU0110 Rev.1.1 Apr 8, 2021 1 2021 Renesas Electronics Corporation V Q6 CC V CC nQ6 CLK SEL Q7 CLK0 nQ7 nCLK0 Q8 V BB nQ8 CLK1 Q9 nCLK1 nQ9 V EE Q10 nQ19 nQ10 Q19 Q11 nQ18 nQ11 Q18 V CC8T33FS6221 DATASHEET Pin Description Table 1. Pin Description Table Number Name Type Description Power supply. All V pins must be connected to the positive power CC 1 V Power CC supply for correct DC and AC operation. Power supply. All V pins must be connected to the positive power CC 2 V Power CC supply for correct DC and AC operation. 3 CLK SEL Input Pull-down Clock reference select input. 4 CLK0 Input Pull-down Differential reference clock signal input. Pull-up/ 5 nCLK0 Input Differential reference clock signal input. Pull-down 6 V Output Reference voltage output for single ended PECL operation. BB 7 CLK1 Input Pull-down Differential reference clock signal input. Pull-up/ 8 nCLK1 Input Differential reference clock signal input. Pull-down 1 9 V Power Negative power supply. EE 10 nQ19 Output PECL Differential clock output. 11 Q19 Output PECL Differential clock output. 12 nQ18 Output PECL Differential clock output. 13 Q18 Output PECL Differential clock output. Power supply. All V pins must be connected to the positive power CC 14 V Power CC supply for correct DC and AC operation. 15 nQ17 Output PECL Differential clock output. 16 Q17 Output PECL Differential clock output. 17 nQ16 Output PECL Differential clock output. 18 Q16 Output PECL Differential clock output. 19 nQ15 Output PECL Differential clock output. 20 Q15 Output PECL Differential clock output. 21 nQ14 Output PECL Differential clock output. 22 Q14 Output PECL Differential clock output. 23 nQ13 Output PECL Differential clock output. 24 Q13 Output PECL Differential clock output. 25 nQ12 Output PECL Differential clock output. 26 Q12 Output PECL Differential clock output. Power supply. All V pins must be connected to the positive power CC 27 V Power CC supply for correct DC and AC operation. 28 nQ11 Output PECL Differential clock output. 29 Q11 Output PECL Differential clock output. 30 nQ10 Output PECL Differential clock output. 31 Q10 Output PECL Differential clock output. 32 nQ9 Output PECL Differential clock output. LOW VOLTAGE 1:20 DIFFERENTIAL PECL/HSTL CLOCK 2 R31DS0008EU0110 Rev.1.1 Apr 8, 2021 FANOUT BUFFER