Low Voltage, 1:15 Differential PECL Clock 8T33FS6222 Divider and Fanout Buffer DATA SHEET General Description Features The 8T33FS6222 is a bipolar monolithic differential clock fanout Fifteen differential PECL outputs (four output banks) buffer. Designed for most demanding clock distribution systems, the Two selectable differential PECL inputs 8T33FS6222 supports various applications that require the Selectable 1 or 2 frequency divider distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very Supports DC to 2GHz input frequency low skew outputs and superior digital signal characteristics. Target Single 3.3V or 2.5V supply applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Standard 52-Lead TQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Functional Description Lead-free RoHS 6 packaging The 8T33FS6222 is designed for low skew clock distribution systems and supports clock frequencies up to 2GHz. The CLK0 and CLK1 inputs can be driven by PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or 2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and are asychronous control inputs. Any changes of the CLK SEL control inputs require a MR pulse for resynchronization of the 2 outputs. For the functionality of the MR control input, see Figure 4.Functional Diagram. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The 8T33FS6222 can be operated from a single 3.3V or 2.5V supply 8T33FS6222 REVISION 1 2/2/15 1 2015 Integrated Device Technology, Inc.8T33FS6222 DATA SHEET . FSELA QA0 0 V V CC EE QA1 CLK0 1 nCLK0 39 38 37 36 35 34 33 32 31 30 29 28 27 40 V 26 QD0 QB0 CC 1 0 0 V EE nQB2 41 25 nQD0 QB1 42 QB2 24 QD1 1 1 V 2 CC QB2 43 nQB1 23 nQD1 CLK1 44 QB1 22 QD2 nCLK1 QC0 0 45 nQB0 21 nQD2 QC1 46 8T33FS6222 QB0 20 QD3 V EE 1 47 CLK SEL V 19 nQD3 CC QC2 48 18 QD4 nQA1 V EE QC3 49 17 QA1 nQD4 50 16 QD5 nQA0 FSELB QD0 FSELC 51 QA0 15 nQD5 QD1 0 52 V 14 V CC CC V EE 123456789 10111213 QD2 MR 1 QD3 V EE QD4 FSELD QD5 52-pin,10mmx10mmTQFPPackage V EE V BB Figure 1. 8T33FS6222 Logic Diagram Figure 2. 52-Lead Package Pin Assignment LOW VOLTAGE, 1:15 DIFFERENTIAL PECL CLOCK 2 REVISION 1 2/2/15 DIVIDER AND FANOUT BUFFER V CC V CC MR QC0 FSELA nQC0 FSELB QC1 CLK0 nQC1 nCLK0 QC2 CLK SEL nQC2 CLK1 QC3 nCLK1 nQC3 V BB V CC FSELC NC FSELD NC V EE V CC