2.5V LVDS 1:16 Clock Fanout Buffer 8T349316 DATASHEET General Description Features The 8T349316 is a 2.5V differential clock buffer with sixteen LVDS Clock signal selection and fanout to 16 LVDS outputs outputs. The fanout from a differential input to the sixteen LVDS Guaranteed Low Skew < 50ps (max) outputs reduces loading on the preceding driver and provides an Low output pulse skew < 125ps (max) efficient clock distribution network. The 8T349316 can act as a translator from a differential HSTL, LVPECL, CML or LVDS input to Propagation delay < 1.75ns (max) LVDS output signals. A single-ended 3.3V, 2.5V LVCMOS/LVTTL Up to 1GHz clock signal operation input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a Support the following input types: HSTL, LVPECL, HCSL, LVTTL primary clock source to a secondary clock source. Selectable Selectable differential input reference inputs are controlled by SEL. The 8T349316 outputs can be asynchronously enabled/disabled. When disabled, the outputs Power-down mode will drive to the value selected by the GL pin. Multiple power and Full 2.5V power supply grounds reduce noise.The extended temperature range supports wireless infrastructure, telecommunication and networking end -40C to +85C ambient operating temperature equipment requirements. The device is a member of the Lead-free (RoHS 6) 52-lead VFQFN-P packaging high-performance clock family from IDT. Replacement device for the 5T9316 Block Diagram Pin Assignment A1 Q1 OUT 1 nA1 CTRL nQ1 Q2 OUT A2 0 CTRL 52 51 50 49 48 47 46 45 44 43 42 41 40 nQ2 nA2 1 39 Q3 nG1 nG2 OUT CTRL nQ3 SEL 2 38 V V DD DD Q4 OUT 3 37 CTRL Q1 Q12 nQ4 GL Q5 OUT 4 36 nQ1 nQ12 CTRL nQ5 5 35 Q2 Q11 Q6 OUT CTRL nQ6 6 34 nQ2 nQ11 Q7 OUT Q3 7 8T349316 33 Q10 CTRL nQ7 Q8 8 32 OUT nQ3 nQ10 CTRL nQ8 nG1 9 31 Q4 Q9 Q9 10 30 OUT nQ4 nQ9 CTRL nG2 nQ9 V 11 29 V DD DD Q10 OUT CTRL 12 28 A1 A2 nQ10 Q11 OUT 13 27 nA1 nA2 CTRL nQ11 14 15 16 17 17 19 20 21 22 23 24 25 26 Q12 OUT CTRL nQ12 Q13 OUT CTRL nQ14 52-lead VFQFN-P, EPad Q15 OUT POWER DOWN CTRL nQ15 8mm x 8mm x 0.9mm Package body nPD CTRL Q16 OUT NL package CTRL nQ16 Top View 8T349316 REVISION 2 11/2/14 1 2014 Integrated Device Technology, Inc. GL SEL V V DD DD Q5 Q16 nQ5 nQ16 Q6 Q15 nQ6 nQ15 Q7 Q14 nQ7 nQ14 Q8 Q13 nQ8 nQ13 V V DD DD GND nPD nc nc8T349316 DATASHEET Pin Description and Pin Characteristic Tables Table 1: Pin Descriptions Number Name Type Description Output enable control input for the Q 1:8 differential outputs. 1 Input - nG1 See Table 3C. LVCMOS/LVTTL interface levels. 2 Power Positive power supply voltage. V DD 3 Output Differential clock output Q1. LVDS interface signals. Q1 4 nQ1 Output Differential clock output Q1. LVDS interface signals. 5 Output Differential clock output Q2. LVDS interface signals. Q2 6 Output Differential clock output Q2. LVDS interface signals. nQ2 7 Q3 Output Differential clock output Q3. LVDS interface signals. 8 Output Differential clock output Q3. LVDS interface signals. nQ3 9 Output Differential clock output Q4. LVDS interface signals. Q4 10 nQ4 Output Differential clock output Q4. LVDS interface signals. 11 Power Positive power supply voltage. V DD 12 Input - Differential clock signal input 1. A1 13 nA1 Input - Differential clock signal input 1. Control input for the output level for outputs in disable state. 14 Input - GL See Table 3C and Table 3D. LVCMOS/LVTTL interface levels. 15 Power Positive power supply voltage. V DD 16 Q5 Output Differential clock output Q5. LVDS interface signals. 17 Output Differential clock output Q5. LVDS interface signals. nQ5 18 Output Differential clock output Q6. LVDS interface signals. Q6 19 nQ6 Output Differential clock output Q6. LVDS interface signals. 20 Output Differential clock output Q7. LVDS interface signals. Q7 21 Output Differential clock output Q7. LVDS interface signals. nQ7 22 Q8 Output Differential clock output Q8. LVDS interface signals. 23 Output Differential clock output Q8. LVDS interface signals. nQ8 24 Power Positive power supply voltage. V DD 25 GND Power Power Supply Ground. 26 - - Not connected. It is recommended to connect this pin to board GND (0V). nc 27 Input - Differential clock signal input 2. nA2 28 A2 Input - Differential clock signal input 2. 29 Power Positive power supply voltage. V DD 30 nQ9 Output Differential clock output Q9. LVDS interface signals. 31 Output Differential clock output Q9. LVDS interface signals. Q9 32 Output Differential clock output Q10. LVDS interface signals. nQ10 33 Q10 Output Differential clock output Q10. LVDS interface signals. 34 Output Differential clock output Q11. LVDS interface signals. nQ11 2.5V LVDS 1:16 CLOCK FANOUT BUFFER 2 REVISION 2 11/2/14