Crystal or Differential to Differential IDT8T39S10I Clock Fanout Buffer DATASHEET General Description Features The IDT8T39S10I is a high-performance clock fanout buffer. The Two differential reference clock input pairs input clock can be selected from two differential inputs or one crystal Differential input pairs can accept the following differential input input. The internal oscillator circuit is automatically disabled if the levels: LVPECL, LVDS, HCSL crystal input is not selected. The crystal pin can be driven by Crystal Oscillator Interface single-ended clock when crystal is bypassed.The selected signal is distributed to ten differential outputs which can be configured as Crystal input frequency range: 10MHz to 40MHz LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is Maximum Output Frequency provided. All outputs can be disabled into a high-impedance state. LVPECL - 2GHz The device is designed for signal fanout of high-frequency, low LVDS - 2GHz phase-noise clock and data signal. The outputs are at a defined level HCSL - 250MHz when inputs are open circuit or tied to ground. It is designed to LVCMOS - 250MHz operate from a 3.3V or 2.5V core power supply, and either a 3.3V or Two banks, each has five differential output pairs that can be 2.5V output operating supply. configured as LVPECL or LVDS or HCSL One single-ended reference output with synchronous enable to avoid clock glitch Output skew: (Bank A and Bank B at the same output level) 70ps (max) Part-to-part skew: 250ps (max) Additive RMS phase jitter: 0.153ps (typical) Supply voltage modes: V /V DD DDO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging IDT8T39S10NLGI REVISION A MARCH 18. 2014 1 2014 Integrated Device Technology, Inc.IDT8T39S10I Data Sheet CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER Block Diagram SMODEA 1:0 Pulldown QA0 nQA0 QA1 REF SEL 1:0 Pulldown nQA1 QA2 nQA2 Pulldown CLK0 QA3 00 nQA3 Pullup/Pulldown nCLK0 QA4 nQA4 Pulldown CLK1 01 Pullup/Pulldown nCLK1 QB0 nQB0 QB1 XTAL IN 10 or nQB1 OSC XTAL OUT 11 QB2 nQB2 QB3 nQB3 IREF QB4 nQB4 Pulldown SMODEB 1:0 REFOUT OE SE Pulldown SYNC Pin Assignment 36 35 34 33 32 31 30 29 28 27 26 25 GND GND 37 24 IREF 38 23 SMODEB0 SMODEB1 39 22 REF SEL1 nCLK1 40 21 nCLK0 IDT8T39S10I CLK1 41 20 CLK0 48-Lead VFQFN V 42 19 REF SEL0 DD 7.0mm x 7.0mm x 0.925mm, package body GND 5.65mm x 5.65mm Epad size 43 18 GND NL Package REFOUT XTAL OUT 44 17 Top View V XTAL IN 45 16 DDO OE SE 46 15 V DD SMODEA1 47 14 SMODEA0 GND 48 13 GND 1234 56789 10 11 12 IDT8T39S10NLGI REVISION A MARCH 18. 2014 2 2013 Integrated Device Technology, Inc. QA0 QB0 nQA0 nQB0 QA1 QB1 nQA1 nQB1 V V DDO DDO QA2 QB2 nQA2 nQB2 V V DDO DDO QA3 QB3 nQA3 nQB3 QA4 QB4 nQA4 nQB4