FemtoClock NG Universal Frequency IDT8T49N222I Translator DATA SHEET General Description Features The IDT8T49N222I is a highly flexible FemtoClock NG general Fourth generation FemtoClock NG technology purpose, low phase noise Frequency Translator / Synthesizer with Universal Frequency Translator alarm and monitoring functions suitable for networking and Zero ppm frequency translation communications applications. It is able to generate any output Two outputs, individually programmable as LVPECL or LVDS frequency in the 7.29MHz to 833.33MHz range and most output Outputs may be individually set to use 2.5V or 3.3V output frequencies in the 925MHz to 1200MHz range (see Table 3A for levels details). A wide range of input reference clocks and a range of Individually programmable output frequencies: 7.29MHz up to low-cost fundamental mode crystal frequencies may be used as the 1200MHz source for the output frequency. Two differential inputs support the following input types: The IDT8T49N222I has three operating modes to support a very LVPECL, LVDS, LVHSTL, HCSL broad spectrum of applications: Input frequency range: 8kHz to 710MHz 1) Frequency Synthesizer Hitless switching between inputs Synthesizes output frequencies from a 16MHz - 40MHz Crystal input frequency range: 16MHz to 40MHz fundamental mode crystal. Holdover support in the event both inputs fail Fractional feedback division is used, so there are no One factory-set register configuration for power-up default state requirements for any specific crystal frequency to produce the desired output frequency with a high degree of accuracy. Configurations customized via One-Time Programmable ROM 2 Settings may be overwritten after power-up via I C 2) High-Bandwidth Frequency Translator 2 I C Serial interface for register programming Applications: PCI Express, Computing, General Purpose RMS phase jitter at 156.25MHz, using a 40MHz crystal Translates any input clock in the 16MHz - 710MHz frequency (12kHz - 20MHz): 507fs (typical), Low Bandwidth Mode (FracN) range into any supported output frequency. Supports ITU-T G.8262 Synchronous Ethernet equipment slave This mode has a high PLL loop bandwidth in order to track input clocks (EEC option 1 and 2) reference changes, such as Spread-Spectrum Clock modulation, so it will not attenuate much jitter on the input Output supply voltage modes: reference. V /V /V CC CCA CCOx 3) Low-Bandwidth Frequency Translator 3.3V/3.3V/3.3V 3.3V/3.3V/2.5V (LVPECL only) Applications: Networking & Communications. 2.5V/2.5V/2.5V Translates any input clock in the 8kHz 710MHz frequency -40C to 85C ambient operating temperature range into any supported output frequency. Available in lead-free (RoHS 6) package This mode supports PLL loop bandwidths in the 10Hz - 580Hz range and makes use of an external crystal to provide significant jitter attenuation. Pin Assignment This device provides a factory-programmed default power-up configuration burned into One-Time Programmable (OTP) memory. The configuration is specified by the customer and is programmed by IDT during the final test phase from an on-hand stock of blank devices. 3635 3433 32 313029 28 27 26 25 CLK ACTIVE 37 24 VEE VEE 38 23 To implement other configurations, these power-up default settings nc 2 LF0 39 C interface and the 22 can be overwritten after power-up using the I VCC IDT8T49N222I LF1 40 21 S AO device can be completely reconfigured. However, these settings 48 Lead VFQFN VEE 41 20 S A1 would have to be written every time the device powers-up. 7.0mm x 7.0mm x 0.925mm, VEE 42 19 Reserved package body nc 43 18 nc NL Package VCCA 44 17 SCLK Top View HOLDOVER 45 16 SDATA CLK0BAD 46 15 VCC CLK1BAD 47 14 PLL BYPASS 48 XTALBAD 13 nc 1 2 3 4 5 6 7 8 9 10 11 12 IDT8T49N222BNLGI REVISION A MAY 13, 2013 1 2013 Integrated Device Technology, Inc. XTAL IN V CCO0 XTAL OUT Q0 VCC nQ0 CLK SEL V EE CLK0 OE0 LOCK IND nCLK0 V VCC EE nc OE1 V VEE EE Q1 VEE CLK1 nQ1 V nCLK1 CCO1IDT8T49N222I Data Sheet FemtoClock NG Universal Frequency Translator Block Diagram PLL BYPASS XTAL IN Output Divider 1 OSC x2 Q0 N0 7:0 0 FemtoClock NG PD/LF 0 XTAL OUT 1 nQ0 VCO OE0 Feedback Divider M INT M FRAC Q1 0 N1 7:0 7:0 17:0 1 nQ1 OE1 ADC LF1 C CLK SEL 3 R 3 4 M1 16:0 CLK0 0 R S PD/CP LF0 nCLK0 P 16:0 CLK1 1 nCLK1 C C P S Status Indicators POR Control Logic CLK ACTIVE Global Registers LOCK IND XTALBAD Register Set CLK0BAD CLK1BAD HOLDOVER SDATA SCLK, S A0, S A1 IDT8T49N222BNLGI REVISION A MAY 13, 2013 2 2013 Integrated Device Technology, Inc. OTP