FemtoClock NG Ultra-Performance 8T49N240 Datasheet Jitter Attenuator Description Features Four differential outputs The 8T49N240 is a fractional-feedback single channel jitter attenuator with frequency translation. It is equipped with three Excellent jitter performance: integer and one fractional output dividers, allowing the generation < 200fs (typical) RMS (including spurs): of up to four different output frequencies, ranging from 8kHz to 12kHz to 20MHz for integer-divider outputs in jitter 867MHz. These frequencies are completely independent of the attenuator mode or in fractional-feedback synthesizer mode input reference frequencies and the crystal reference frequency. Operating Modes: Synthesizer, Jitter Attenuator The outputs may select among LVPECL, LVDS, HCSL, or Operates from a 10MHz to 54MHz fundamental-mode crystal LVCMOS output levels. Initial holdover accuracy of +50ppb The 8T49N240 accepts up to two differential or single-ended input Accepts up to two LVPECL, LVDS, LVHSTL, or LVCMOS input clocks and a fundamental-mode crystal input. The internal PLL clocks can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer. The PLL can use the Accepts frequencies ranging from 8kHz to 875MHz second input for redundant backup of the primary input reference, Auto and manual clock selection with hitless switching but in this case, both input clock references must be integer Clock input monitoring including support for gapped clocks related in frequency. Phase-slope limiting and fully hitless switching options to The device supports hitless reference switching between input control output clock phase transients clocks. The device monitors both input clocks for Loss of Signal Three outputs generate LVPECL / LVDS / HCSL clocks, one (LOS), and generates an alarm when an input clock failure is output generates LVPECL / LVDS / HCSL / LVCMOS clocks detected. Automatic and manual hitless reference switching Output frequencies ranging from 8kHz up to 867MHz options are supported. LOS behavior can be set to support (differential) gapped or un-gapped clocks. Output frequencies ranging from 8kHz to 250MHz The 8T49N240 supports holdover. The holdover has an initial (LVCMOS) accuracy of 50ppB from the point where the loss of all applicable Three integer dividers with fixed divider ratios (see Table 3) input reference(s) has been detected. It maintains a historical One fractional output divider average operating point for the PLL that may be returned to in holdover at a limited phase slope. Programmable loop bandwidth settings from 0.2Hz to 6.4kHz Optional fast-lock function The PLL has a register-selectable loop bandwidth from 0.2Hz to 6.4kHz. Four General Purpose I/O pins with optional support for status and control: The device supports Output Enable and Clock Select inputs and Two Output Enable control inputs provide control over the Lock, Holdover, and LOS status outputs. four clocks 2 The device is programmable through an I C interface. It also Manual clock selection control input 2 supports I C master capability to allow the register configuration Lock, Holdover, and Loss-of-Signal alarm outputs to be read from an external EEPROM. Open-drain Interrupt pin Factory pre-programmed devices are also available using the 2 2 Register programmable through I C or via external I C on-chip One Time Programmable (OTP) memory. EEPROM Full 2.5V or 3.3V supply modes, with some support for 1.8V Typical Applications -40C to 85C ambient operating temperature OTN, including ITU-T G.709 (2009) FEC Package: 6 x 6 x 0.9 mm 40-VFQFN, lead-free (RoHS 6) CPRI interfaces Fiber optics 40G/100G Ethernet Gb Ethernet, Terabit IP switches / routers 2019 Integrated Device Technology, Inc. 1 January 15, 20198T49N240 Datasheet Contents Description 1 Typical Applications . 1 Features 1 Block Diagram . 4 Pin Assignments 5 Pin Descriptions 5 Principles of Operation . 8 Crystal Input 8 Bypass Path 8 Input Clock Selection . 9 Input Clock Monitor . 9 Holdover 10 Input to Output Clock Frequency . 10 Synthesizer Mode Operation . 10 Loop Filter and Bandwidth 11 Integer Output Dividers (Q0, Q1 or Q2) 11 Fractional Output Divider Programming (Q3 Only) 11 Output Divider Frequency Sources 11 Output Phase Control on Switchover 12 Output Drivers 12 LVCMOS Operation (Q3 Only) . 12 Power-Saving Modes 12 Status / Control Signals and Interrupts . 12 General-Purpose I/Os and Interrupts 13 Interrupt Functionality 13 Output Enable Operation . 13 Device Hardware Configuration 14 Device Start-up and Reset Behavior . 14 Serial Control Port Description . 15 Serial Control Port Configuration Description 15 I2C Mode Operation . 15 I2C Master Mode . 16 I2C Boot-up Initialization Mode . 17 Absolute Maximum Ratings 40 Supply Voltage Characteristics . 40 DC Electrical Characteristics . 42 AC Electrical Characteristics . 45 Typical Phase Noise at 156.25MHz . 52 Applications Information . 53 Recommendations for Unused Input and Output Pins . 53 Inputs 53 Outputs . 53 Overdriving the XTAL Interface . 54 Wiring the Differential Input to Accept Single-Ended Levels . 55 3.3V Differential Clock Input Interface 56 2.5V Differential Clock Input Interface 57 LVDS Driver Termination . 58 Termination for 3.3V LVPECL Outputs . 59 2019 Integrated Device Technology, Inc. 2 January 15, 2019