FemtoClock NG Universal Frequency 8T49N241 Datasheet Translator Description Typical Applications The 8T49N241 has one fractional-feedback PLL that can be used as OTN or SONET / SDH equipment a jitter attenuator and frequency translator. It is equipped with one Gigabit and Terabit IP switches / routers including Synchronous integer and three fractional output dividers, allowing the generation of Ethernet up to four different output frequencies, ranging from 8kHz to 1GHz. Video broadcast These frequencies are completely independent of each other, the input reference frequencies, and the crystal reference frequency. The device places virtually no constraints on input to output frequency Features conversion, supporting all FEC rates, including the new revision of Supports SDH/SONET and Synchronous Ethernet clocks including ITU-T Recommendation G.709 (2009), most with 0ppm conversion all FEC rate conversions error. The outputs may select among LVPECL, LVDS, HCSL or 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz LVCMOS output levels. Operating Modes: Synthesizer, Jitter Attenuator This makes it ideal to be used in any frequency synthesis application, Operates from a 10MHz to 50MHz fundamental-mode crystal or a including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and 10MHz to 125MHz external oscillator SONET/SDH, including ITU-T G.709 (2009) FEC rates. Initial holdover accuracy of +50ppb. The 8T49N241 accepts up to two differential or single-ended input Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks clocks and a fundamental-mode crystal input. The internal PLL can Accepts frequencies ranging from 8kHz to 875MHz lock to either of the input reference clocks or just to the crystal to Auto and manual clock selection with hitless switching behave as a frequency synthesizer. The PLL can use the second Clock input monitoring including support for gapped clocks input for redundant backup of the primary input reference, but in this case, both input clock references must be related in frequency. Phase-slope limiting and fully hitless switching options to control output clock phase transients The device supports hitless reference switching between input Generates four LVPECL / LVDS / HCSL or eight LVCMOS output clocks. The device monitors both input clocks for Loss of Signal clocks (LOS), and generates an alarm when an input clock failure is Output frequencies ranging from 8kHz up to 1.0GHz detected. Automatic and manual hitless reference switching options (differential) are supported. LOS behavior can be set to support gapped or Output frequencies ranging from 8kHz to 250MHz (LVCMOS) un-gapped clocks. One integer divider ranging from 4 to 786,420 The 8T49N241 supports holdover. The holdover has an initial Three fractional output dividers (see Output Dividers) accuracy of 50ppB from the point where the loss of all applicable Programmable loop bandwidth settings from 0.2Hz to 6.4kHz input reference(s) has been detected. It maintains a historical Optional fast-lock function average operating point for the PLL that may be returned to in holdover at a limited phase slope. Four General Purpose I/O pins with optional support for status & control: The PLL has a register-selectable loop bandwidth from 0.2Hz to Two Output Enable control inputs provide control over the four 6.4kHz. clocks The device supports Output Enable & Clock Select inputs and Lock, Manual clock selection control input Holdover & LOS status outputs. Lock, Holdover and Loss-of-Signal alarm outputs 2 The device is programmable through an I C interface. It also supports Open-drain Interrupt pin 2 2 2 I C master capability to allow the register configuration to be read Register programmable through I C or via external I C EEPROM from an external EEPROM. Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs, Programming with IDTs Timing Commander software is GPIO and control pins recommended for optimal device performance. Factory -40C to 85C ambient operating temperature pre-programmed devices are also available. Package: 40-VFQFPN, lead-free (RoHS 6) 2019 Integrated Device Technology, Inc. 1 March 5, 20198T49N241 Datasheet 8T49N241 Block Diagram Q0 IntN Divider CLK0 Input Clock P0 Monitoring, FracN Priority, Feedback & PLL Selection Q1 P1 CLK1 FracN Divider XTAL OSC FracN Divider Q2 Reset nRST Logic FracN Divider Q3 Status & GPIO Control Logic OTP 2 Registers I C Master SCLK 4 2 I C Slave SDATA nINT Serial EEPROM GPIO nWP S A 1:0 Figure 1. 8T49N241 Block Diagram 2019 Integrated Device Technology, Inc. 2 March 5, 2019