FemtoClock NG Universal Frequency 8T49N242 Datasheet Translator Description Typical Applications The 8T49N242 has one fractional-feedback PLL that can be used as OTN or SONET / SDH equipment a jitter attenuator and frequency translator. It is equipped with four Gigabit and Terabit IP switches / routers including Synchronous integer output dividers, allowing the generation of up to four different Ethernet output frequencies, ranging from 8kHz to 1GHz. These frequencies Video broadcast are completely independent of the input reference frequencies, and the crystal reference frequency. The device places virtually no constraints on input to output frequency conversion, supporting all Features FEC rates, including the new revision of ITU-T Recommendation Supports SDH/SONET and Synchronous Ethernet clocks including G.709 (2009), most with 0ppm conversion error. The outputs may all FEC rate conversions select among LVPECL, LVDS, HCSL or LVCMOS output levels. 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz This makes it ideal to be used in any frequency synthesis application, Operating Modes: Synthesizer, Jitter Attenuator including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and Operates from a 10MHz to 50MHz fundamental-mode crystal or a SONET/SDH, including ITU-T G.709 (2009) FEC rates. 10MHz to 125MHz external oscillator The 8T49N242 accepts up to two differential or single-ended input Initial holdover accuracy of +50ppb. clocks and a fundamental-mode crystal input. The internal PLL can Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks lock to either of the input reference clocks or just to the crystal to Accepts frequencies ranging from 8kHz to 875MHz behave as a frequency synthesizer. The PLL can use the second Auto and manual clock selection with hitless switching input for redundant backup of the primary input reference, but in this Clock input monitoring including support for gapped clocks case, both input clock references must be related in frequency. Phase-slope limiting and fully hitless switching options to control The device supports hitless reference switching between input output clock phase transients clocks. The device monitors both input clocks for Loss of Signal Generates four LVPECL / LVDS / HCSL or eight LVCMOS output (LOS), and generates an alarm when an input clock failure is clocks detected. Automatic and manual hitless reference switching options Output frequencies ranging from 8kHz up to 1.0GHz are supported. LOS behavior can be set to support gapped or (differential) un-gapped clocks. Output frequencies ranging from 8kHz to 250MHz (LVCMOS) The 8T49N242 supports holdover. The holdover has an initial Integer divider ranging from 4 to 786,420 for each output accuracy of 50ppB from the point where the loss of all applicable Programmable loop bandwidth settings from 0.2Hz to 6.4kHz input reference(s) has been detected. It maintains a historical Optional fast-lock function average operating point for the PLL that may be returned to in holdover at a limited phase slope. Four General Purpose I/O pins with optional support for status & control: The PLL has a register-selectable loop bandwidth from 0.2Hz to Two Output Enable control inputs provide control over the four 6.4kHz. clocks The device supports Output Enable & Clock Select inputs and Lock, Manual clock selection control input Holdover & LOS status outputs. Lock, Holdover and Loss-of-Signal alarm outputs 2 Open-drain Interrupt pin The device is programmable through an I C interface. It also supports 2 2 2 I C master capability to allow the register configuration to be read Register programmable through I C or via external I C EEPROM from an external EEPROM. Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs, GPIO and control pins Programming with IDTs Timing Commander software is recommended for optimal device performance. Factory -40C to 85C ambient operating temperature pre-programmed devices are also available. Package: 40-VFQFPN, lead-free (RoHS 6) 2019 Integrated Device Technology, Inc. 1 January 16, 20198T49N242 Datasheet 8T49N242 Block Diagram Q0 IntN Divider Input Clock P0 CLK0 Monitoring, FracN Priority, Feedback PLL & P1 CLK1 Selection Q1 IntN Divider XTAL OSC IntN Divider Q2 Reset nRST Logic IntN Divider Q3 Status & GPIO Control Logic OTP 2 Registers I C Master SCLK 4 2 I C Slave SDATA nINT Serial EEPROM GPIO nWP S A 1:0 Figure 1. 8T49N242 Block Diagram 2019 Integrated Device Technology, Inc. 2 January 16, 2019