FemtoClock NG Octal Universal 8T49N281 Frequency Translator Datasheet Description Features The 8T49N281 has a fractional-feedback PLL that can be used as a Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions jitter attenuator or frequency translator. It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 Two differential outputs meet jitter limits for 100G Ethernet and different output frequencies, ranging from 8kHz to 1GHz. Three of STM-256/OC-768 these frequencies are completely independent of each other and the <0.3ps RMS (including spurs): 12kHz to 20MHz inputs. The other five are related frequencies. The eight outputs may All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz select among LVPECL, LVDS or LVCMOS output levels. Operating modes: locked to input signal, holdover and free-run This functionality makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Initial holdover accuracy of 50ppb Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS G.709 (2009) FEC rates. The device may also behave as a frequency input clocks synthesizer. Accepts frequencies ranging from 8kHz up to 875MHz The 8T49N281 accepts up to two differential or single-ended input Auto and manual input clock selection with hitless switching clocks and a crystal input. The PLL can lock to either input clock, but both input clocks must be related in frequency. Clock input monitoring, including support for gapped clocks Phase-Slope Limiting and Fully Hitless Switching options to The device supports hitless reference switching between input control output phase transients clocks. The device monitors both input clocks for Loss of Signal (LOS). It generates an alarm when an input clock failure is detected. Operates from a 10MHz to 40MHz fundamental-mode crystal Automatic and manual hitless reference switching options are Generates eight LVPECL /LVDS or sixteen LVCMOS output supported. LOS behavior can be set to support gapped or un-gapped clocks clocks. Output frequencies ranging from 8kHz up to 1.0GHz (diff) The 8T49N281 supports holdover with an initial accuracy of 50ppB Output frequencies ranging from 8kHz to 250MHz (LVCMOS) from the point where the loss of all applicable input reference(s) has been detected. It maintains a historical average operating point that Four General Purpose I/O pins with optional support for status & may be returned to in holdover at a limited phase slope. control: The device places no constraints on input to output frequency Four Output Enable control inputs may be mapped to any of the eight outputs conversion, supporting all FEC rates, including the new revision of ITU-T Recommendation G.709 (2009), most with 0ppm conversion Lock, Holdover & Loss-of-Signal status outputs error. Open-drain Interrupt pin The PLL has a register-selectable loop bandwidth from 0.5Hz to Programmable PLL bandwidth settings: 512Hz. 0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz Each output supports individual phase delay settings to allow or 512Hz output-output alignment. Optional Fast Lock function The device supports Output Enable inputs and Lock, Holdover and Programmable output phase delays in steps as small as 16ps LOS status outputs. 2 2 2 Register programmable through I C or via external I C EEPROM The device is programmable through an I C interface. It also supports 2 I C master capability to allow the register configuration to be read Bypass clock paths for system tests from an external EEPROM. Power supply modes V / V / V CC CCA CCO 3.3V / 3.3V / 3.3V Typical Applications 3.3V / 3.3V / 2.5V 3.3V / 3.3V / 1.8V (LVCMOS) OTN or SONET / SDH equipment Line cards (up to OC-192, and 2.5V / 2.5V / 3.3V supporting FEC ratios) 2.5V / 2.5V / 2.5V OTN de-mapping (Gapped Clock and DCO mode) 2.5V / 2.5V / 1.8V (LVCMOS) Gigabit and Terabit IP switches / routers including support of Power down modes support consumption as low as 1.5W (see Synchronous Ethernet Power Dissipation and Thermal Considerations for details) Wireless base station baseband -40C to 85C ambient operating temperature Data communications Package: 56QFN, lead-free RoHs (6) 2019 Integrated Device Technology, Inc. 1 January 17, 20198T49N281 Datasheet 8T49N281 Block Diagram XTAL IntN Output OSC Q0 Input Clock Fractional Divider Monitoring, Feedback Priority, APLL IntN Output Clk0 P0 Q1 & Divider Lock Clk1 P1 Selection Holdover FracN Output Q2 Divider FracN Output Q3 Divider IntN Q4 Reset nRST IntN Q5 LOS Logic Status Registers GPIO Logic OTP 2 IntN Q6 I C Master Control Registers SCLK 4 2 I C Slave SDATA IntN Q7 Serial EEPROM PLL BYP SA0 nINT GPIO Figure 1. 8T49N281 Functional Block Diagram 2019 Integrated Device Technology, Inc. 2 January 17, 2019