FemtoClock NG Octal Universal 8T49N283 Frequency Translator Datasheet Description Features The 8T49N283 has two independent, fractional-feedback PLLs that Supports SDH/SONET and Synchronous Ethernet clocks can be used as jitter attenuators and frequency translators. It is including all FEC rate conversions equipped with six integer and two fractional output dividers, allowing Two differential outputs meet jitter limits for 100G Ethernet and the generation of up to 8 different output frequencies, ranging from STM-256/OC-768 8kHz to 1GHz. Four of these frequencies are completely independent <0.3ps RMS (including spurs): 12kHz to 20MHz of each other and the inputs. The other four are related frequencies. All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz The eight outputs may select among LVPECL, LVDS or LVCMOS output levels. Operating modes: locked to input signal, holdover and free-run Initial holdover accuracy of 50ppb This makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, Accepts up to two LVPECL, LVDS, LVHSTL or LVCMOS input clocks OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The device may also behave as a frequency synthesizer. Accepts frequencies ranging from 8kHz up to 875MHz Auto and manual input clock selection with hitless switching The 8T49N283 accepts up to two differential or single-ended input Clock input monitoring, including support for gapped clocks clocks and a crystal input. Each of the two internal PLLs can lock to Phase-Slope Limiting and Fully Hitless Switching options to different input clocks which may be of independent frequencies. Each control output phase transients PLL can use the other input for redundant backup of the primary clock, but in this case, both input clocks must be related in frequency. Operates from a 10MHz to 40MHz fundamental-mode crystal Generates eight LVPECL / LVDS or sixteen LVCMOS output The device supports hitless reference switching between input clocks clocks. The device monitors all input clocks for Loss of Signal (LOS), Output frequencies ranging from 8kHz up to 1.0GHz (diff) and generates an alarm when an input clock failure is detected. Automatic and manual hitless reference switching options are Output frequencies ranging from 8kHz to 250MHz (LVCMOS) supported. LOS behavior can be set to support gapped or un-gapped Four General Purpose I/O pins with optional support for status & control: clocks. Four Output Enable control inputs may be mapped to any of the The 8T49N283 supports holdover for each PLL. The holdover has an eight outputs initial accuracy of 50ppB from the point where the loss of all Lock, Holdover & Loss-of-Signal status outputs applicable input reference(s) has been detected. It maintains a Open-drain Interrupt pin historical average operating point for each PLL that may be returned to in holdover at a limited phase slope. Programmable PLL bandwidth settings for each PLL: 0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz The device places no constraints on input to output frequency or 512Hz conversion, supporting all FEC rates, including the new revision of Optional Fast Lock function ITU-T Recommendation G.709 (2009), most with 0ppm conversion Programmable output phase delays in steps as small as 16ps error. 2 2 Register programmable through I C or via external I C EEPROM Each PLL has a register-selectable loop bandwidth from 0.5Hz to Bypass clock paths for system tests 512Hz. Power supply modes Each output supports individual phase delay settings to allow V / V / V CC CCA CCO output-output alignment. 3.3V / 3.3V / 3.3V The device supports Output Enable inputs and Lock, Holdover and 3.3V / 3.3V / 2.5V LOS status outputs. 3.3V / 3.3V / 1.8V (LVCMOS) 2 2.5V / 2.5V / 3.3V The device is programmable through an I C interface. It also supports 2 2.5V / 2.5V / 2.5V I C master capability to allow the register configuration to be read 2.5V / 2.5V / 1.8V (LVCMOS) from an external EEPROM. Power down modes support consumption as low as 1.7W (see Typical Applications Power Dissipation and Thermal Considerations for details) -40C to 85C ambient operating temperature OTN or SONET / SDH equipment Line cards (up to OC-192, and supporting FEC ratios) Package: 56QFN, lead-free (RoHS 6) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet Wireless base station baseband Data communications 2019 Integrated Device Technology, Inc. 1 January 29, 20198T49N283 Datasheet 8T49N283 Block Diagram IntN Output Q0 Fractional Divider Feedback XTAL APLL 0 IntN Output OSC Q1 Divider Lock 0 Input Clock Holdover 0 Monitoring, FracN Output Clk0 P0 Priority, Q2 Divider Fractional & Clk1 P1 Feedback Selection APLL 1 FracN Output Q3 Divider Lock 1 Holdover 1 IntN Q4 Reset nRST IntN Q5 LOS Logic Status Registers GPIO OTP Logic 2 IntN I C Master Q6 Control Registers SCLK 4 2 I C Slave SDATA Q7 IntN Serial EEPROM PLL BYP SA0 GPIO nINT Figure 1. 8T49N283 Functional Block Diagram 2019 Integrated Device Technology, Inc. 2 January 29, 2019