8T53S111NLGI Renesas

IDT8T53S111I 1:10 LVPECL Output Fanout Buffer DATA SHEET General Description Features The IDT8T53S111I is a high-performance differential LVPECL fanout Ten low skew, low additive jitter LVPECL outputs buffer. The device is designed for the fanout of high-frequency, very Two selectable, differential LVPECL clock inputs low additive phase-noise clock and data signals. The IDT8T53S111I Differential pairs can accept the following differential input is characterized to operate from a 3.3V and 2.5V power supply. levels: LVDS, LVPECL and CML Guaranteed output-to-output and part-to-part skew characteristics Maximum input clock frequency: 2.5GHz make the IDT8T53S111I ideal for those clock distribution LVCMOS interface levels for the control input (input select) applications demanding well-defined performance and repeatability. Two selectable differential inputs and ten low skew outputs are Output skew: 15ps (typical) available. The integrated V voltage generator enables easy REF Propagation delay: 250ps (typical) interfacing of single-ended signals to the device inputs. The device is Additive phase jitter, RMS f = 156.25MHz (12kHz - 20MHz): REF optimized for low power consumption and low additive phase noise. 30fs (typical) Full 3.3V and 2.5V supply voltage Maximum device current consumption (I ): 126mA EE Lead-free (RoHS 6) 32-Lead VFQFN package -40C to 85C ambient operating temperature Block Diagram Pin Assignment Q0 nQ0 24 23 22 21 20 19 18 17 25 16 VCCO VCCO Q1 nQ2 26 15 Q7 nQ1 Q2 27 14 nQ7 Q2 nQ1 28 13 Q8 nQ2 Q1 29 12 nQ8 nQ0 11 30 Q9 Pulldown Q3 PCLK0 Q0 nQ9 31 10 nQ3 PU / PD nPCLK0 VCCO 32 9 VCCO 12 3 4 5 6 7 8 Q4 0 nQ4 Q5 1 nQ5 Pulldown IDT8T53S111I PCLK1 Q6 32-lead VFQFN PU / PD nPCLK1 nQ6 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm E-Pad Q7 NL Package, Top View nQ7 Pulldown SEL Q8 VOLTAGE V REF nQ8 REFERENCE Q9 nQ9 IDT8T53S111NLGI REVISION A JULY 12, 2012 1 2012 Integrated Device Technology, Inc. V Q3 CC SEL nQ3 PCLK0 Q4 nQ4 nP C LK 0 VR E F Q5 PCLK1 nQ5 nP C LK 1 Q6 VEE nQ6IDT8T53S111I Data Sheet 1:10 LVPECL OUTPUT FANOUTBUFFER Table 1. Pin Descriptions Number Name Type Description 1V Power Power supply pin. CC Reference select control. See Table 3 for function. LVCMOS/LVTTL interface 2 SEL Input Pulldown levels. 3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock/data input. Pulldown/ 4 nPCLK0 Input Inverting differential LVPECL clock input. Pullup Bias voltage generator for the nPCLK 0:1 inputs in single-ended input signal 5V Output REF applications. 6 PCLK1 Input Pulldown Non-inverting differential LVPECL clock/data input. Pulldown/ 7 nPCLK1 Input Inverting differential LVPECL clock input. Pullup 8V Power Negative power supply pin. EE 9, 16, V Power Output power supply pins. CCO 25, 32 10, 11 nQ9, Q9 Output Differential output pair. LVPECL interface levels. 12, 13 nQ8, Q8 Output Differential output pair. LVPECL interface levels. 14, 15 nQ7, Q7 Output Differential output pair. LVPECL interface levels. 17, 18 nQ6, Q6 Output Differential output pair. LVPECL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2 pF C IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Function Table Table 3A. SEL Input Selection Function Table Input SEL Operation 0 (default) PCLK0, nPCLK0 is the selected differential clock input. 1 PCLK1, nPCLK1 is the selected differential clock input. NOTE: SEL is an asynchronous control. IDT8T53S111NLGI REVISION A JULY 12, 2012 2 2012 Integrated Device Technology, Inc.