2.5 V, 3.3 V Differential LVPECL 8T73S208 Clock Divider and Fanout Buffer Datasheet General Description Features The 8T73S208 is a high-performance differential LVPECL clock One differential input reference clock divider and fanout buffer. The device is designed for the frequency Differential pair can accept the following differential input division and signal fanout of high-frequency, low phase-noise clocks. levels: LVDS, LVPECL, CML The 8T73S208 is characterized to operate from a 2.5V and 3.3V Integrated input termination resistors power supply. Guaranteed output-to-output and part-to-part skew Eight LVPECL outputs characteristics make the 8T73S208 ideal for those clock distribution Selectable clock frequency division of 1, 2, 4 and 8 applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the Maximum input clock frequency: 1000MHz reference source easy and reduce passive component count. Each LVCMOS interface levels for the control inputs output can be individually enabled or disabled in the high-impedance 2 2 Individual output enable/disabled by I C interface C register. On power-up, all outputs are state controlled by a I enabled. Output skew: 15ps (typical) Output rise/fall times: 350ps (maximum) Low additive phase jitter, RMS: 0.182ps (typical) Full 2.5V and 3.3V supply voltages Lead-free (RoHS 6) 32-Lead VFQFN packaging -40C to 85C ambient operating temperature Block Diagram Pin Assignment Q0 nQ0 Q1 24 23 22 21 20 19 18 17 nQ1 25 16 FSEL1 nQ5 f REF IN Q2 26 15 1, 2, Q5 IN nIN nQ2 4, 8 27 14 V nQ4 T 50 50 Q3 28 13 nIN Q4 VT nQ3 8T73S208 29 12 V nQ3 CC Pulldown (2) FSEL 1:0 Q4 2 30 11 SDA Q3 nQ4 31 10 nQ2 SCL Q5 32 9 nQ5 ADR0 Q2 2 Pullup I C SDA 12345678 Pullup 8 SCL Q6 Pulldown (2) ADR 1:0 nQ6 2 Q7 nQ7 32-pin, 5mm x 5mm VFQFN 2016 Integrated Device Technology, Inc. 1 Revision D, June 15, 2016 ADR1 FSEL0 V V EE EE Q0 nQ7 nQ0 Q7 Q1 nQ6 nQ1 Q6 V V EE EE V V CCO CCO8T73S208 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 ADR1, ADR0 Input Pulldown I C Address inputs. LVCMOS/LVTTL interface levels. 32 2, 7, 18, 23 V Power Negative supply pins. EE 3, 4 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 5, 6 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. 8, 17 V Power Output supply pins. CCO 9, 10 Q2, nQ2 Output Differential output pair 2. LVPECL interface levels. 11, 12 Q3, nQ3 Output Differential output pair 3. LVPECL interface levels. 13, 14 Q4, nQ4 Output Differential output pair 4. LVPECL interface levels. 15, 16 Q5, nQ5 Output Differential output pair 5. LVPECL interface levels. 19, 20 Q6, nQ6 Output Differential output pair 6. LVPECL interface levels. 21, 22 Q7, nQ7 Output Differential output pair 7. LVPECL interface levels. 24, FSEL0, Frequency divider select controls. See Table 3A for function. Input Pulldown 25 FSEL1 LVCMOS/LVTTL interface levels. 26 IN Input Non-inverting differential clock input. RT = 50 termination to V T. Termination Input for termination. Both IN and nIN inputs are internally terminated 50 27 V T Input to this pin. See input termination information in the applications section. 28 nIN Input Inverting differential clock input. RT = 50 termination to V T. 29 V Power Power supply pin. CC 2 I C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output: 30 SDA I/O Pullup open drain. 2 31 SCL Input Pullup I C Clock Input. LVCMOS/LVTTL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN Input Pulldown Resistor 51 k R PULLDOWN R Input Pullup Resistor 51 k PULLUP 2016 Integrated Device Technology, Inc. 2 Revision D, June 15, 2016