FemtoClock NG Jitter Attenuator 8V19N492 and Clock Synthesizer Datasheet Description Features High-performance clock RF-PLL with support for JESD204B The 8V19N492 is a fully integrated FemtoClock NG jitter attenuator and clock synthesizer designed as a high-performance Optimized for low phase noise: -150dBc/Hz (800kHz offset clock solution for conditioning and frequency/phase management 245.76MHz clock) of wireless base station radio equipment boards. The device is Integrated phase noise of 80fs RMS typical (12k-20MHz). optimized to deliver excellent phase noise performance as Dual-PLL architecture required in GSM, WCDMA, LTE, and LTE-A radio board 1st-PLL stage with external VCXO for clock jitter attenuation implementations. The device supports JESD204B subclass 0 and 1 clocks. 2nd-PLL with internal FemtoClockNG PLL: 2949.12MHz Six output channels with a total of 16 outputs, organized in: A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator Four JESD204B channels (device clock and SYSREF and uses an external VCXO for best possible phase noise output) with two, four and five outputs characteristics. The second stage PLL locks on the VCXO-PLL One clock channel with two outputs output signal and synthesizes the target frequency. One VCXO output The device supports the clock generation of high-frequency clocks Configurable integer clock frequency dividers from the selected VCO and low-frequency synchronization signals Supported clock output frequencies include: 2949.12, 1474.56, (SYSREF). SYSREF signals are internally synchronized to the 983.04, 491.52, 245.76, and 122.88MHz clock signals. Delay functions exist for achieving alignment and Low-power LVPECL/LVDS outputs support configurable signal controlled phase delay between system reference and clock amplitude, DC and AC coupling and LVPECL, LVDS line signals and to align/delay individual output signals. The four terminations techniques redundant inputs are monitored for activity. Four selectable clock Phase delay circuits switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency Clock phase delay with 256 steps of 339ps and a range of dividers, and phase adjustment capabilities are added for 0 to 86.466ns flexibility. Individual SYSREF phase delay with 8 steps of 169ps The device is configured through a three-wire SPI interface and Additional individual SYSREF fine phase delay with 25ps reports lock and signal loss status in internal registers and via a steps lock detect (LOCK) output. Internal status bit changes can also be Global SYSREF signal delay with 256 steps of 339ps and a reported via the nINT output. The 8V19N492 is ideal for driving range of 0 to 86.466 ns converter circuits in wireless infrastructure, radar/imaging, and Redundant input clock architecture with two inputs and instrumentation/medical applications. The device is a member of Input activity monitoring the high-performance clock family from Renesas. Manual and automatic, fault-triggered clock selection modes Priority controlled clock selection Typical Applications Digital holdover and hitless switching Wireless infrastructure applications: GSM, WCDMA, LTE, Differential inputs accept LVDS and LVPECL signals and LTE-A SYSREF generation modes include internal and external Ideal clock driver for jitter-sensitive ADC and DAC circuits trigger mode for JESD204B Low phase noise clock generation Supply voltage: 3.3V Ethernet line cards SPI and control I/O voltage: 1.8V/3.3V (Selectable) Radar and imaging Package: 10 x 10 mm 88-VFQFPN Instrumentation and medical Temperature range: -40C to +105C (Case) 2020 Renesas Electronics Corporation 1 November 5, 20208V19N492 Datasheet Block Diagram Figure 1. Block Diagram (f = 2949.12MHz) VCO VCXO-PLL QCLK V Loo p Fi lter nQCLK V R0 CLK 0 Clock C1 VDD LCF nCLK 0 C0 Monitor BYPV FDF PV PF OSC and PFD CLK 1 CR Selector CP nCLK 1 LFV nOSC PFD CR x2 CP MV0 f VCXO fVCO ICPF FemtoClockNG LFF BYPF MF C2 M V1 C3 FemtoClockNG PLL Loo p Filter R1 Holdover LFFR QCLK A 1:0 NA nQCLK A 1:0 CLK A 2 NS QREF A0 REF S nQREF A0 MUX A0 REF A0 QREF A1 nQREF A1 SYSREF EXT SYS MUX A1 REF A1 Generator QREF A2 nQREF A2 REF A2 MUX A2 Channel A QCLK B 1:0 NB nQCLK B 1:0 CLK B 2 QREF B0 nQREF B0 REF B0 MUX B0 QREF B1 nQREF B1 MUX B1 REF B1 Channel B QCLK C N C nQCLK C CLK C QREF C nQREF C REF C MUX C Channel C QCLK D N D nQCLK D CLK D QREF D nQREF D MUX D REF D Channel D QCLK E0 NE nQCLK E0 CLK E QCLK E1 nQCLK E1 Channel E SDAT SPI SCLK nINT Register File LOCK nCS SELSV 2020 Renesas Electronics Corporation 2 November 5, 2020