Radio Unit Clock Synchronizer and 8V19N850D Converter Clock Generator Datasheet Description Features High-performance radio clock synchronizer clock The 8V19N850 is a fully integrated Radio Unit Clock Synchronizer and Converter Clock Generator designed as a high-performance clock Device clock domain (RF-PLL) with support for JESD204B/C solution for phase/frequency synchronization and signal conditioning of Digital clock domain (Ethernet, FEC) with support for eEEC wireless base station radio equipment. The device supports and T-BC/T-TSC Class C JESD204B/C subclass 0 and 1 device clocks and SYSREF 2 differential clock reference inputs synchronization for converters. 1PPS (1Hz) to 1GHz input frequency The 8V19N850 supports two independent frequency domains: one that Dual DPLL front-end with independent clock paths can be used for the digital clock (Ethernet and FEC rates) domain with External control of the DCO for IEEE1588 four outputs, and the device clock (RF-PLL) domain with 12 outputs. The -7 Ethernet domain generates frequencies from two independent APLLs Digital holdover with a 1.1 10 ppb accuracy for flexibility the outputs of the RF clock domain generate very low Programmable DPLL loop bandwidth 1mHz - 6kHz phase noise clocks for ADC/DAC circuits. Configurable phase delay (range: 1UI) From the integrated RF-PLL, the device supports the clock generation of Hitless input switching with < 1ns output phase error high-frequency device clocks for driving ADC/DAC devices Reference monitors for input LOS, activity and frequency low-frequency synchronization signals (SYSREF). 1 external synchronization input for JESD204B/C (LVCMOS) A dual DPLL front-end architecture supports any frequency translation. 16 differential outputs Each DPLL provides a programmable bandwidth and a DCO function for Dedicated phase management capabilities real-time frequency/phase adjustments. The DPLLs can lock on 1PPS input signals and establish lock within 100s or less. Frequency Optimized for low phase noise: information can be applied from DPLL-0 to DPLL-1 and vice versa to Device clocks: -149.9dBc/Hz (1MHz offset 245.76MHz clock) enable the combining of the frequency characteristics of two references Supply voltage (core): 3.3V (outputs): 3.3V, 2.5V, and 1.8V (combo-mode). Package: 10 10 mm 88-VFQFPN SM The 8V19N850 is configured through a pin-mapped I3C (including Board temperature range: -40C to +105C 2 2 legacy I C) and 3/4-wire SPI interface. I C with master capabilities reads a default configuration from an external ROM device. GPIO ports Applicable Standards can be configured for reporting and controlling purposes. ITU-T G.8262 EEC1/2, G.8262.1 eEEC Applications ITU-T G.8273.2 T-BC/T-TSC Class C JESD204B and C Wireless infrastructure 5G radio Simplified Block Diagram TCXO/OCXO SYS DPLL 4 Output Channels 4 Differential Frequency Dividers Clock 0 DPLL-0/APLL-0 APLL-2 Clock Outputs Phase Delay 4 1GHz 6 RF Output Channels Clock 1 DPLL-1/APLL-1 RF-PLL 6 Differential Clock + SYSREF Clock Outputs 6 Frequency Dividers 2.94912 GHz Phase Delay SYSREF SYSREF 6 Differential Generator SYSREF Outputs 6 DCO Cmds Register 2 I3C/I C/SPI 2021 Renesas Electronics Corporation 1 May 18, 20218V19N850 Datasheet Block Diagram Figure 1. Block Diagram OSCI XTAL OSC SYS-APLL System Clocks OSCO QCLK D0 ND0 nQCLK D0 Integer XO DPLL TCXO SYS-DPLL Combo Bus QCLK D1 nXO PLL ND1 nQCLK D1 GbE clock Integer QCLK D2 GbE+FEC clock ND2 nQCLK D2 APLL-0 LOS, Freq. CLK 0 DPLL-0 3.6-3.868 Integer APLL-2 2.45- Monitor GHz nCLK 0 (DCO-0) 2.58GHz QCLK D3 ND3 REF0 nQCLK D3 Integer Combo Bus Ref. Switching State QCLK R0 Machines NR0 nQCLK R0 Integer Device clock QREF R0 nQREF R0 LOS, Freq. DPLL-1 APLL-1 2.94912 CLK 1 RF-PLL (DCO-1) 3.93216GHz Monitor GHz QCLK R1 nCLK 1 REF1 nQCLK R1 QREF R1 Combo Bus nQREF R1 SYSREF RF-PLL Channel 0 EXT SYS Generator QCLK R2 N R1 nQCLK R2 SYSREF Integer QREF R2 nQREF R2 QCLK R3 nQCLK R3 QREF R3 nQREF R3 RF-PLL Channel 1 QCLK R4 Device Settings & DCO Control NR2 nQCLK R4 SDI/ADR1 Integer SDO/SDA 2 I3C/I C/SPI Register File GPIO QREF R4 SCLK/SCL nCS/ADR0 nQREF R4 SPI SEL RF-PLL Channel 2 QCLK R5 Boot Configuration N R3 nQCLK R5 SDA M 2 I C Master Integer SCL M QREF R5 nQREF R5 GPIO 0:3 RF-PLL Channel 3 2021 Renesas Electronics Corporation 2 May 18, 2021