8V34S204NLGI Renesas

1:4 LVDS Fanout Buffer with 2-Input 8V34S204 Multiplexer for 1PPS Applications DATA SHEET General Description Features The 8V34S204 is a differential 1:4 LVDS fanout buffer with a 2:1 input Designed for 1PPS, 2kHz, 8kHz and 10MHz GPS clock signal multiplexer. The device accepts DC to 250MHz clock and data distribution signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal High speed 1:4 LVDS fanout buffer distribution. Controlled by the input mode selection pin, the differential input stages accept both rectangular or sinusoidal signals. Four differential LVDS output pairs The 8V34S204 also provides level translated LVCMOS/LVTTL 2:1 input multiplexer outputs which are copies of the individual differential inputs CLKA and CLKB. The propagation delay of the device is very low, providing Two selectable differential inputs accept LVDS and LVPECL signals an ideal solution for clock distribution circuits with tight phase Accepts rectangular and sinusoidal input signals alignment requirements. The multiplexer select pin (SEL) allows to select one out of two input signals, which is copied to the four Two input monitoring outputs (LVCMOS) differential outputs. Max Output frequency: 250MHz Additive phase jitter, RMS 12kHz to 20MHz: = 65fs at 156.25MHz (typical) Part-to-part skew: 200ps (maximum) Propagation delay (differential outputs): 350ps (typical) Full 2.5V and 3.3V voltage supply -40C to 85C ambient operating temperature Lead-free 24-lead VFQFN (RoHS 6/6) packaging Block Diagram Pin Assignment QA Pulldown Q0 CLKA 0 nQ0 Pullup/Pulldown nCLKA (default) Q1 nQ1 Q2 Pulldown nQ2 CLKB 1 Pullup/Pulldown nCLKB Q3 nQ3 Pulldown MODE Pulldown SEL Pulldown SVS 24-LeadVFQFN QB 4mm x 4mm x 0.9mm NL Package TopView 8V34S204 REVISION 1 6/17/14 1 2014 Integrated Device Technology, Inc.8V34S204 DATA SHEET Pin Description and Pin Characteristic Tables 1 Table 1. Pin Descriptions Number Name Type Description 1 CLKA Input Pulldown Non-inverting differential clock input. Pullup/ 2 nCLKA Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 3 MODE Input Pulldown Input mode pin. See Table 3B. LVCMOS/LVTTL interface levels. 4 SEL Input Pulldown Input selection pin. See Table 3A. LVCMOS/LVTTL interface levels. 5 CLKB Input Pulldown Non-inverting differential clock input. Pullup/ 6 nCLKB Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 7 SVS Input Pulldown Supply Voltage Select. See Table 3C. LVCMOS/LVTTL interface levels. Power Output supply pin for the QB output. 8V DDO B 9 QB Output Single-ended output clock. LVCMOS/LVTTL interface levels. 10 GND Power Power supply ground. Power Power supply pins for the device core. 11 V DD 12 Q0 Output Differential output pair. LVDS interface levels. 13 nQ0 Output Differential output pair. LVDS interface levels. 14 Q1 Output Differential output pair. LVDS interface levels. 15 nQ1 Output Differential output pair. LVDS interface levels. 16 Q2 Output Differential output pair. LVDS interface levels. 17 nQ2 Output Differential output pair. LVDS interface levels. 18 Q3 Output Differential output pair. LVDS interface levels. 19 nQ3 Output Differential output pair. LVDS interface levels. Power Power supply pins for the device core. 20 V DD 21 GND Power Power supply ground. 22 QA Output Single-ended output clock. LVCMOS/LVTTL interface levels. Power Output supply pin for the QA output. 23 V DDO A 24 GND Power Power supply ground. NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1:4 LVDS FANOUT BUFFER WITH 2-INPUT MULTIPLEXER FOR 2 REVISION 1 6/17/14 1PPS APPLICATIONS