FemtoClock NG Crystal-to-HCSL IDT8V41N004I Clock Generator DATA SHEET General Description Features The IDT8V41N004I is a clock generator designed for Gigabit Fourth generation FemtoClock NG technology Ethernet, 10 Gigabit Ethernet, SGMII and PCI Express Four 100MHz, 125MHz, 156.25MHz and 312.5MHz clocks for applications. The device generates a selectable 100MHz, 125MHz, Gigabit Ethernet, 10 Gigabit Ethernet, SGMII and PCI Express applications, HCSL interface levels 156.25MHz or 312.5MHz clock signal from 25MHz input. The NG IDT8V41N004I uses IDTs fourth generation FemtoClock Selectable external crystal or differential input source technology to provide low phase noise performance, combined with Crystal oscillator interface designed for 25MHz parallel excellent power supply noise rejection for optimal performance in the resonant crystal targeted applications. The device supports a 3.3V supply voltage and Differential CLK, nCLK input pair accepts LVPECL, LVDS, is packaged in a compact, lead-free (RoHS 6) 32-lead VFQFN LVHSTL, HCSL input levels package. The industrial temperature range supports high end Internal resistor bias on nCLK pin allows the user to drive CLK computing, telecommunication and networking end equipment input with external single-ended (LVCMOS/ LVTTL) input levels requirements. PCI Express Gen1, Gen2, and Gen 3 compliant RMS phase jitter 156.25MHz (12kHz - 20MHz): 0.217ps Full 3.3V supply voltage -40C to 85C ambient operating temperature Pin Assignment 24 23 22 21 20 19 18 17 25 GND 16 FSEL1 26 15 FSEL0 nQ0 27 Q0 14 V DD 28 V 13 XTAL OUT DD IDT8V41N004I 29 12 OE3 XTAL IN OE2 30 11 CLK SEL 31 V 10 DD nREF OUT V 32 9 DDA REF OUT 12 3 4 5 6 7 8 32 Lead VFQFN 5mm x 5mm x 0.925mm Package Body 3.15mm x 3.15mm EPad Size NL Package Top View IDT8V41N004NLGI REVISION A DECEMBER 18, 2012 1 2012 Integrated Device Technology, Inc. Q1 PLL BYPASS nQ1 OE REF V DD OE1 Q2 OE0 nQ2 IREF GND V DD Q3 CLK nQ3 nCK IDT8V41N004I Data Sheet FEMTOCLOCK NG CRYSTAL-TO-HCSL CLOCK GENERATOR Block Diagram Pulldown OE REF REF OUT nREF OUT Pulldown Q0 CLK SEL nQ0 Q1 1 XTAL IN nQ1 FSEL 1:0 0 OSC Q2 FemtoClock NG 00 16 XTAL OUT PLL x2 0 01 25 nQ2 Pulldown CLK 2.5GHz 10 20 1 PU/PD Q3 11 8 nCLK nQ3 IREF Pulldown FSEL1 Pulldown FSEL0 Pulldown PLL BYPASS Pulldown OE0 Pulldown OE1 Pulldown OE2 Pulldown OE3 IDT8V41N004NLGI REVISION A DECEMBER 18, 2012 2 2012 Integrated Device Technology, Inc.