3
Clock Generator for Cavium Processors
8V41N012
Datasheet
General Description Features
The 8V41N012 is a PLL-based clock generator specifically designed Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
for Cavium Networks Octeon II processors. This high performance
device is optimized to generate the processor core reference clock,
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
the PCI-Express, sRIO, XAUI, SerDes reference clocks and the
One single-ended QF LVCMOS/LVTTL clock output at 50MHz
clocks for both the Gigabit Ethernet MAC and PHY. The output fre-
quencies are generated from a 25MHz external input source or an
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz
external 25MHz parallel resonant crystal. The industrial temperature
Selectable external crystal or differential (single-ended)
range of the 8V41N012 supports telecommunication, networking,
input source
and storage requirements.
Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
Pin Assignment
-40C to 85C ambient operating temperature
Lead-free (RoHS 6) packaging
54 45 53 52 51 50 49 48 47 46 44 43 42 41 40 39 3837
55
QE0 36 GND
56 nQB1
nQE0 35
QE1 57 34 QB1
nQE1 58 33 nQB0
GND 59 32 QB0
60 V
OE_E 31 DDO_QB
61
FSEL_C0 30 OE_A
8V41N012
FSEL_C1 62 GND
29
63
GND 28 nQA1
V 64 27 QA1
DDA
FSEL_D0
65 nQA0
26
FSEL_D1 66 25 QA0
V 67 V
DD 24 DDO_QA
nMR 68 GND
23
VDDO_QG 69 22 V
DD
QG 70 GND
21
GND 71 QF
20
OE_G 72 V
19 DDO_QF
1 2 4 5 6 7 8 9 10 11 12 13 1415161718
72-Lead, 10mm x 10mm VFQFN
NOTE: Exposed pad must always be connected to GND.
NOTE: Pin 1 is located at bottom left corner as shown.
2016 Integrated Device Technology, Inc. 1 Revison C, November 2, 2016
OE_REF VDDO_QE
VDDO_QREF IREF
QREF0 OE_D
QREF1 GND
GND nQD1
QD1
FSEL_E0
FSEL_E1 nQD0
QD0
REF_SEL
VDDO_QD
VDD
XTAL_IN VDD
XTAL_OUT OE_C
PLL_SEL GND
FSEL_A0 nQC1
FSEL_A1 QC1
CLK nQC0
n CLK QC0
FSEL_B0 VDDO_QC
FSEL_B1 OE_B8V41N012 Datasheet
Block Diagram
Pulldown
nMR
Pullup
OE_A
QA0
00 = 100MHz
nQA0
01 = 125MHz
10 = 156.25MHz
QA1
11 = 312.5MHz
nQA1
Pullup
OE_B
QB0
00 = 100MHz
Pulldown 2
FSEL_A[1:0]
nQB0
01 = 125MHz
10 = 156.25MHz
2
Pulldown QB1
FSEL_B[1:0]
11 = 312.5MHz
Clock
nQB1
Pulldown
2 Output
FSEL_C[1:0]
Pullup
Control
OE_C
Pulldown 2 Logic
FSEL_D[1:0] QC0
00 = 100MHz
2
Pulldown
nQC0
01 = 125MHz
FSEL_E[1:0]
10 = 156.25MHz
QC1
11 = 312.5MHz
nQC1
Pullup
OE_D
QD0
00 = 100MHz
Pullup nQD0
01 = 125MHz
PLL_SEL
10 = 156.25MHz
QD1
11 = 312.5MHz
nQD1
Pullup
REF_SEL
Pullup
OE_E
XTAL_IN
QE0
00 = 100MHz
OSC
nQE0
01 = 125MHz
1
XTAL_OUT 10 = 156.25MHz
QE1
FemtoClock NG
11 = 312.5MHz
1
VCO
nQE1
0
Pulldown
CLK
0
PU/PD
50MHz QF
nCLK
Pullup
OE_G
I_REF
125MHz QG
Pullup
OE_REF
QREF0
QREF1
2016 Integrated Device Technology, Inc. 2 Revison C, November 2, 2016