FemtoClock NG Ultra Low Jitter 8V41NS0412 HCSL Clock Generator Datasheet Description Features Eleven differential HCSL outputs The 8V41NS0412 is a clock generator with four output dividers: three integer, and one that is either integer or fractional. When One LVCMOS output input reference can be bypassed to this used with an external crystal, the 8V41NS0412 generates high output performance timing geared towards the communications and The clock input operates in full differential mode (LVDS, datacom markets, especially for applications demanding LVPECL) or single-ended LVCMOS mode extremely low phase noise, such as 10GE, 40GE, 100G, and Driven from a crystal or differential clock input 400GE. A 2.4 2.5GHz PLL frequency range supports Ethernet, The 8V41NS0412s versatile frequency configurations are SONET, and CPRI frequency plans optimized to deliver excellent phase noise performance. The 1.25GHz maximum output frequency device delivers an optimum combination of high clock frequency Four integer output dividers with a range of output divide ratios and low-phase noise performance, combined with high-power (see Table 5) supply noise rejection. One fractional output divider can generate any desired output The 8V41NS0412 supports HCSL type of output level on eleven of frequency its outputs. In addition, there is a single LVCMOS output that has Support of output power-down the option of providing a generated clock or acting as a reference bypass output. Excellent clock output phase noise Offset Output Frequency Single-side Band Phase Noise The device can be configured to deliver specific configurations 100kHz 156.25MHz -143dBc/Hz 2 under pin control only, or additional configurations through an I C Phase noise RMS, 156.25MHz, 12kHz to 20MHz integration serial interface by an external processor. range: 80fs (typical) The 8V41NS0412 is offered in a lead-free (RoHS6) 64-VFQFN Selected configurations can be controlled via the use of control package. input pins without need for serial port access 2 LVCMOS compatible I C serial interface gives access to Typical Applications additional configurations by external processor or in combination with the control input pins PCI Express Clocking Single 3.3V supply voltage 10G/40G/100G/400G Ethernet Lead-free (RoHS 6) 64-VFQFN packaging Gb Ethernet, Terabit IP switches / routers -40C to 85C ambient operating temperature CPRI Interfaces Fiber Optics 2020 Renesas Electronics Corporation 1 August 27, 20208V41NS0412 Datasheet Block Diagram Figure 1. 8V41NS0412 Block Diagram REF SEL LOCK CLK QA0 nCLK FDP 24002500MHz and QA1 PLL PS IntN Div A OSCI OSC QA2 OSCO QA3 M FIN 1:0 QB0 NA 1:0 QB1 IntN Div B Status and Control QB2 NB 1:0 Registers QB3 NC 1:0 ND 1:0 QC0 IntN Div C QC1 Power On Reset IntN Div D SCLK QD0 FracN Div D FDIV I2C Slave SDATA QD1 8V41NS0412 transistor count: 131,496 2020 Renesas Electronics Corporation 2 August 27, 2020