91305AGILF Renesas

ICS91305 High Performance Communication Buffer General Description Features The ICS91305 is a high performance, low skew, low jitter Zero input - output delay clock driver. It uses a phase lock loop (PLL) technology Frequency range 10 - 133 MHz (3.3V) to align, in both phase and frequency, the REF input with 5V tolerant input REF the CLKOUT signal. It is designed to distribute high speed High loop filter bandwidth ideal for Spread clocks in communication systems operating at speeds Spectrum applications. from 10 to 133 MHz. Less than 200 ps Jitter between outputs Skew controlled outputs ICS91305 is a zero delay buffer that provides Skew less than 250 ps between outputs synchronization between the input and output. The synchronization is established via CLKOUT feed back to Available in 8 pin 150 mil SOIC & 173 mil the input of the PLL. Since the skew between the input and TSSOP packages output is less than +/- 350 pS, the part acts as a zero delay 3.3V 10% operation buffer. The ICS91305 comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Block Diagram Pin Configuration REF 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 VDD GND 4 5 CLK3 8 pin SOIC & TSSOP 0092H12/02/08 ICS91305ICS91305 Pin Descriptions PEIN NUMBERPEIN NAMTNYP DESCRIPTIO 2 1FREI.N Input reference frequency, 5V tolerant input 3 22CLKOtUT Buffered clock outpu 3 31CLKOtUT Buffered clock outpu 4DGRN PdW Groun 3 53CLKOtUT Buffered clock outpu 6DVRDP)W Power Supply (3.3V 3 74CLKOtUT Buffered clock outpu 3 8TCLKOUOnUT Buffered clock output. Internal feedback on this pi Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 0092H12/02/08 2