ICS93716 Low Cost DDR Phase Lock Loop Clock Driver Recommended Application: Pin Configuration DDR Clock Driver CLKC0 1 28 GND CLKT0 2 27 CLKC5 Product Description/Features: VDD 3 26 CLKT5 Low skew, low jitter PLL clock driver CLKT1 4 25 CLKC4 2 CLKC1 5 24 CLKT4 I C for functional and output control GND 6 23 VDD Feedback pins for input to output synchronization SCLK 7 22 SDATA Spread Spectrum tolerant inputs CLK INT 8 21 FBINC CLK INC 9 20 FBINT Bypass mode on B revision only VDDA 10 19 FB OUTT GND 11 18 FB OUTC VDD 12 17 CLKT3 Switching Characteristics: CLKT2 13 16 CLKC3 PEAK - PEAK jitter (66MHz): <75ps CLKC2 14 15 GND CYCLE - CYCLE jitter (>100MHz):<65ps OUTPUT - OUTPUT skew: <100ps 28-Pin SSOP and TSSOP Output Rise and Fall Time: 550ps - 950ps Functionality ISNPUTS OUTPUT PLL State ATVDDCCLK INCTLK INCCLKCTLKFCB OUT FB OUT 2.5V LH L H L H on (nom) 2.5V HL H L H L on (nom) 2.5V <Z20MHz ZZ Z off (nom) GLND H L H L H Bypassed/off Block Diagram GHND L H L H L Bypassed/off FB OUTT FB OUTC Control CLKT0 SCLK CLKC0 Logic SDATA CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 FB INT CLKC3 FB INC PLL CLK INC CLKT4 CLKC4 CLK INT CLKT5 CLKC5 0420H09/10/08 ICS93716 ICS93716 Pin Descriptions PEIN NUMBERPEIN NAMTNYP DESCRIPTIO 6D, 11, 15, 28GRN PdW Groun 2)7, 25, 16, 14, 5, 1CTLKC(5:0O.UComplementar clocks of differential pair outputs 2)6, 24, 17, 13, 4, 2CTLKT(5:0O.UTru Clock of differential pair outputs 3D, 12, 23VRD PVW Power supply 2.5 2 7SNCLK IIClock input of C input, 5V tolerant input 8TCNLK INITru reference clock inpu 9CCNLK INIComplementar reference clock inpu 1A0VRDDPVW Analog power supply, 2.5Complementar Feedback output, dedicated for external feedback. It 1C8FTB OUT OU switches at the same frequency as the CLK. This output must be wired to FB INC.Tru Feedback output, dedicated for external feedback. It switches 1T9FTB OUT OU at the same frequency as the CLK. This output must be wired to FB INT.Tru Feedback input, provides feedback signal to the internal PLL for 2T0FNB IN I synchronization with CLK INT to eliminate phase error.Complementar Feedback input, provides signal to the internal PLL 2C1FNB IN I for synchronization with CLK INC to eliminate phase error. 2 22 SNDATA IIData input for C serial input, 5V tolerant input 0420H09/10/08 2