ICS950810 Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock for BANIAS processor/ ODEM and Pin Configuration MONTARA-G chipsets. 156 VDDREF REF X1255 FS1 X2354 FS0 Output Features: 453 GND CPU STOP * 3 0.7V Differential CPU Clock Pairs PCICLK F0552 CPUCLKT0 7 PCI (3.3V) 33.3MHz PCICLK F1651 CPUCLKC0 750 PCICLK F2 VDDCPU 3 PCI F (3.3V) 33.3MHz VDDPCI849 CPUCLKT1 1 USB (3.3V) 48MHz GND948 CPUCLKC1 PCICLK0 10 47 GND 1 DOT (3.3V) 48MHz PCICLK1 11 46 VDDCPU 1 REF (3.3V) 14.318MHz PCICLK2 12 45 CPUCLKT2 5 3V66 (3.3V) 66.6MHz 13 44 PCICLK3 CPUCLKC2 VDDPCI 14 43 MULTSEL0* 1 VCH/3V66 (3.3V) 48MHz or 66.6MHz GND 15 42 IREF 16 41 PCICLK4 GND PCICLK5 17 40 FS2 Features: PCICLK6 18 39 48MHz USB Supports spread spectrum modulation, VDD3V66 19 38 48MHz DOT down spread 0 to -0.5%. (CPU, 3V66, PCI) GND 20 37 VDD48 3V66 2 21 36 GND Efficient power management scheme through PD , 3V66 3 22 35 3V66 1/VCH CLK CPU STOP and PCI STOP . 3V66 4 23 34 PCI STOP * 3V66 5 24 33 3V66 0 25 32 Key Specifications: *PD VDD3V66 VDDA 26 31 GND CPU Output Jitter <150ps GND 27 30 SCLK 3V66 Output Jitter <250ps 28 29 Vtt PWRGD SDATA CPU Output Skew <100ps 56-Pin 300mil SSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP * These inputs have 150K internal pull-up resistor to VDD. Block Diagram Functionality PCI F CPU 3V66(5:0) 48MHz USB PLL2 F1S2F0S FS PCI (MHz) (MHz) (MHz) 48MHz DOT X0 01666.66636.6 33.3 X1 XTAL 3V66 5 X0 11600.00636.6 33.3 OSC X2 3V66 3 X1 02600.00636.6 33.3 3V66 (4,2) X1 11633.33636.6 33.3 PLL1 REF M0id 0TeristateTeristat Tristat Spread CPU CPUCLKT (2:0) Spectrum 3 Stop DIVDER M0id 1T4CLK/2T8CLK/ TCLK/ CPUCLKC (2:0) 3 M1id 0RdeservedRdeserve Reserve PCI Stop PCICLK (6:0) PD DIVDER 7 M1id 1RdeservedRdeserve Reserve Control CPU STOP PCICLK F (2:0) 3V66 3 PCI STOP DIVDER Logic MULTSEL0 3V66 0 FS (2:0) 3V66 1/VCH CLK Config. SDATA Reg. SCLK I REF 0472F01/12/04 ICS950810ICS950810 Pin Configuration PIN PEIN NAMETNYP DESCRIPTIO NUMBER 1FVRDDREPVW Ref, XTAL power supply, nominal 3.3 21XNI.Crystal input,nominally 14.318MHz 32XTO.U Crystal output, nominally 14.318MHz 4 GRNDP.W Ground pin for 3V outputs 50PTCICLK FO.U Free running PCI clock not affected by PCI STOP 61PTCICLK FO.U Free running PCI clock not affected by PCI STOP 72PTCICLK FO.U Free running PCI clock not affected by PCI STOP 8IVRDDPCPVW Power supply for PCICLK F and PCICLK, nominal 3.3 9DGRNP.W Ground pin for 3V outputs 100PTCICLK O.U PCI clock outputs 111PTCICLK O.U PCI clock outputs 122 PCICLKO.UT PCI clock outputs 133 PCICLK O.UT PCI clock outputs 1I4 VDDPC PWR Power supply for PCICLK F and PCICLK, nominal 3.3V 1D5 GRNP.W Ground pin for 3V outputs 146PTCICLK O.U PCI clock outputs 157PTCICLK O.U PCI clock outputs 168PTCICLK O.U PCI clock outputs 169VRDD3V6P.W Power pin for the 3V66 clocks 2D0 GRNP.W Ground pin for 3V outputs 2213TV66 O.U 66MHz outputs at 3.3V 232 3TV66 O.U 66MHz outputs at 3.3V 2433TV66 O.U 66MHz outputs at 3.3V 2543TV66 O.U 66MHz input/output at 3.3V Asynchronous active low input pin used to power down the device into a low 2 5 PND I power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 2A6 VRDDP.W 3.3V power for the PLL core 2D7 GRNP.W Ground pin for 3V outputs 0472F01/12/04 2