Integrated ICS952906A Circuit Systems, Inc. Programmable Timing Control Hub for Next Gen P4 processor Recommended Application: Features/Benefits: VIA VN800/CN700/P4M800 style chipset for P4 processor Programmable output frequency. Programmable asynchronous 3V66&PCI frequency. Output Features: Programmable output divider ratios. 3 - 0.7V current-mode differential CPU pairs Programmable output skew. 10 - PCI, 3 free running, 33MHz Programmable spread percentage for EMI control. 2 - REF, 14.318MHz Watchdog timer technology to reset system if system malfunctions. 3 - 3V66, 66.66MHz Programmable watch dog safe frequency. 1 - 48MHz Support I2C Index read/write and block read/write 1 - 24/48MHz operations. 2 - 25MHz 2.5V Uses external 14.318MHz reference input. Key Specifications: CPU/SRC outputs cycle-cycle jitter < 125ps 3V66 outputs cycle-cycle jitter < 250ps PCI outputs cycle-cycle jitter < 250ps CPU - AGP skew < +/- 350ps AGP-PCI skew between 1~3.5ns Functionality Pin Configuration Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP PCI *FS1/REF0 1 48 VDDA **FS0/REF1 2 47 GND FS4FS3 FS2FS1 FS0 MHz MHz MHz 100.00 66.67 33.33 VDDREF 3 46 IREF 000 00 X1 4 45 CPUCLKT ITP/(PCI STOP ) 000 01 200.00 66.67 33.33 X2 5 44 CPUCLKC ITP/(CPU STOP ) 000 10 133.33 66.67 33.33 GND 6 43 GND 000 11 166.67 66.67 33.33 **FS2/PCICLK F0 7 42 CPUCLKT1 001 00 200.00 66.67 33.33 **FS4/PCICLK F1 8 41 CPUCLKC1 001 01 400.00 66.67 33.33 PCICLK F2 9 40 VDDCPU 001 10 266.67 66.67 33.33 10 39 CPUCLKT0 VDDPCI 001 11 333.33 66.67 33.33 11 38 CPUCLKC0 GND 100.99 67.33 33.66 12 37 010 00 **MODE/PCICLK0 GND 13 36 25Mhz 0 201.98 67.33 33.66 PCICLK1 010 01 PCICLK2 14 35 25Mhz 1 134.65 67.33 33.66 010 10 PCICLK3 15 34 VDD2.5 010 11 168.31 67.32 33.66 PCICLK4 16 33 VttPWR GD/PD 01 1 00 115.00 76.67 38.33 VDDPCI 17 32 SDATA 011 01 230.00 76.67 38.33 GND 18 31 SCLK 153.33 76.66 38.33 011 10 PCICLK5 19 30 Reset 191.67 76.67 38.33 011 11 20 29 PCICLK6 3V66 0 1 100.00 66.66 33.33 00 00 21 28 **FS3/48MHz GND 200.00 66.66 33.33 **Sel24 48 /24 48MHz 22 27 VDD3V66 100 01 23 26 133.33 66.66 33.33 GND 3V66 1 100 10 24 25 3V66 2 VDD48 166.67 71.43 35.71 100 11 * This pin have 120K pull-up to VDD 01 00 200.00 66.66 33.33 1 ** This pin have 120K pull-down to GND 101 01 400.00 66.66 33.33 101 10 266.67 66.66 33.33 101 11 333.33 66.66 33.33 48-pin SSOP & TSSOP 105.00 69.99 35.00 110 00 210.00 69.99 35.00 110 01 140.00 69.99 35.00 110 10 175.00 69.99 35.00 110 11 1 110.00 73.33 36.66 11 00 220.00 73.33 36.66 111 01 111 10 146.66 73.33 36.66 111 11 183.34 73.33 36.66 1236A08/06/07 ICS952906Integrated ICS952906A Circuit Systems, Inc. Pin Description PIN PIN NAME PIN TYPE DESCRIPTION 1 *FS1/REF0 I/O Frequency select latch input pin / 14.318 MHz reference clock. 2 **FS0/REF1 I/O Frequency select latch input pin / 14.318 MHz reference clock. 3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 4 X1 IN Crystal input, Nominally 14.318MHz. 5 X2 OUT Crystal output, Nominally 14.318MHz 6 GND PWR Ground pin. 7 **FS2/PCICLK F0 I/O Frequency select latch input pin / 3.3V PCI free running clock output. 8 **FS4/PCICLK F1 I/O Frequency select latch input pin / 3.3V PCI free running clock output. 9 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 11 GND PWR Ground pin. Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP 12 **MODE/PCICLK0 I/O inputs) / PCI clock output. 13 PCICLK1 OUT PCI clock output. 14 PCICLK2 OUT PCI clock output. 15 PCICLK3 OUT PCI clock output. 16 PCICLK4 OUT PCI clock output. 17 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 18 GND PWR Ground pin. 19 PCICLK5 OUT PCI clock output. 20 PCICLK6 OUT PCI clock output. 21 **FS3/48MHz I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 22 **Sel24 48 /24 48MHz I/O Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. 23 GND PWR Ground pin. 24 VDD48 PWR Power pin for the 48MHz output.3.3V 25 3V66 2 OUT 3.3V 66.66MHz clock output 26 3V66 1 OUT 3.3V 66.66MHz clock output 27 VDD3V66 PWR Power pin for the 3.3V 66MHz clocks. 28 GND PWR Ground pin. 29 3V66 0 OUT 3.3V 66.66MHz clock output Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is 30 Reset OUT active low. 31 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 32 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant. This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready 33 VttPWR GD/PD IN to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. 34 VDD2.5 PWR Power supply, nominal 2.5V 35 25Mhz 1 OUT 25MHz clock output, 2.5V 36 25Mhz 0 OUT 25MHz clock output, 2.5V 37 GND PWR Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors 38 CPUCLKC0 OUT are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required 39 CPUCLKT0 OUT for voltage bias. 40 VDDCPU PWR Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors 41 CPUCLKC1 OUT are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required 42 CPUCLKT1 OUT for voltage bias. 43 GND PWR Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors 44 CPUCLKC ITP/(CPU STOP ) I/O are required for voltage bias. / Stops all CPUCLK besides the free running clocks True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required 45 CPUCLKT ITP/(PCI STOP ) I/O for voltage bias. / Stops all PCICLK besides the free running clocks This pin establishes the reference current for the differential current-mode output pairs. This pin requires a 46 IREF OUT fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 GND PWR Ground pin. 48 VDDA PWR 3.3V power for the PLL core. 1236A08/06/07 2