ICS95V847 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) Recommended Application: Pin Configuration Zero Delay Board Fan Out, SO-DIMM Provides complete DDR registered DIMM solution 24 CLKT4 GND 1 with ICSSSTV16857, ICSSSTV16859 or CLKC0 2 23 CLKC4 ICSSSTV32852 CLKT0 3 22 CLKC3 GND 4 21 CLKT3 Product Description/Features: VDD 5 20 VDD Low skew, low jitter PLL clock driver CLK INT 6 19 FB INT CLK INC 7 18 FB INC 1 to 5 differential clock distribution (SSTL 2) AVDD 8 17 FB OUTC Feedback pins for input to output synchronization AGND 9 16 FB OUTT Spread Spectrum tolerant inputs CLKC1 10 15 CLKT2 CLKT1 11 14 CLKC2 VDD 12 13 GND Switching Characteristics: CYCLE - CYCLE jitter: <60ps OUTPUT - OUTPUT skew: <60ps 24-Pin TSSOP Period jitter: 30ps 4.40 mm. Body, 0.65 mm. pitch DUTY CYCLE: 49.5% - 50.5% Functionality Block Diagram ISNPUTS OUTPUT PLL State FB OUTT ATVDDCCLK INCTLK INCCLKCTLKFCB OUT FB OUT FB OUTC GLND H L H L H Bypassed/off CLKT0 FB INT GHND L H L H L Bypassed/off CLKC0 FB INC PLL CLK INC 2.5V CLKT1 LH LH L H on (nom) CLK INT CLKC1 2.5V HL HL H L on CLKT2 (nom) CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 0718E11/24/08 ICS95V847ICS95V847 Pin Descriptions PEIN NUMBERPEIN NAMTNYP DESCRIPTIO 5D, 12, 20VRD PVW Power supply, 2.5 1D, 4, 13GRN PdW Groun 8DARVD PVW Analog power supply, 2.5 9DARGN PdW Analog groun 3 , 11, 15, 21, 24CTLKT 0:4OsUTru Clock of differential pair output 2 , 10, 14, 22, 23CTLKC 0:4OsUComplementar clocks of differential pair output 6TCNLK INITru reference clock inpu 7CCNLK INIComplementar reference clock inpuTru Feedback output, dedicated for external feedback. It switches 1T6FTB OUT OU at the same frequency as the CLK. This output must be wired to FB INTComplementar Feedback output, dedicated for external feedback. It 1C7FTB OUT OU switches at the same frequency as the CLK. This output must be wired to FB INCTru Feedback input, provides feedback signal to the internal PLL for 1T9FNB IN I synchronization with CLK INT to eliminate phase errorComplementar Feedback input, provides signal to the internal PLL 1C8FNB IN I for synchronization with CLK INC to eliminate phase error This PLL Clock Buffer is designed for a V of 2.5V, an AV of 2.5V and differential data input and output levels. DD DD ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK INT, CLK INC) to five differential pair of clock outputs (CLKT 4:0 , CLKC 4:0 ) and one differential pair feedback clock output (FB OUT, FB OUTC). The clock outputs are controlled by input clock (CLK INT, CLK INC), the feedback clock (FB INT, FB INC) and the analog power input (AV ). When AV is grounded, the PLL is turned off and bypassed for test purposes. DD DD The PLL in ICS95V847 clock driver uses the input clock (CLK INC, CLK INT) and the feedback clock (FB INT, FB INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT 4:0 , CLKC 4:0 ). ICS95V847 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. ICS95V847 is characterized for operation from 0C to 85C. 0718E11/24/08 2