ICS97ULP8 45A Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: Pin Configuration DDR2 Memory Modules / Zero Delay Buffer Fan Out Provides complete DDR DIMM logic solution 1 2 345 A Product Description/Features: Low skew, low jitter PLL clock driver B 1 to 5 differential clock distribution (SSTL 18) C Feedback pins for input to output synchronization D Spread Spectrum tolerant inputs E Auto PD when input signal is at a certain logic state F Switching Characteristics: Period jitter: 40ps Half-period jitter: 60ps CYCLE - CYCLE jitter 40ps 28-Ball BGA OUTPUT - OUTPUT skew: 40ps Top View Block Diagram Ball Assignments CLKT0 CLKC0 OE LD* or OE 12 34 5 Powerdown CLKT1 OS Control and CLKC1 A CLKT0 CLKC0 CLKC1 CLKT1 FB INT Test Logic AV DD CLKT2 PLL bypass CLKC2 B CK INT V NB V FB INC LD* DD DD CLKT3 CLKC3 C CK INC OE V OS FB OUTC DD CLKT4 D AGND GND V GND FB OUTT CLKC4 DD E AVDD GND NB GND CLKT2 CLK INT CLK INC F CLKC4 CLKT4 CLKC3 CLKT3 CLKC2 FB OUTT FB OUTC 10K-100k PLL GND FB INT FB INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK INT and CLK INC. 1109D06/19/07ICS97ULP845A Pin Descriptions Terminal Electrical Description Name Characteristics AdGND Analog Groun Ground AV Analog power 1.8 V nominal DD CrLK INT Clock input with a (10K-100K Ohm) pulldown resisto Differential input CLK INC Complentary clock input with a (10K-100K Ohm) pulldown resistor Differential input FtB INT Feedback clock inpu Differential input FtB INC Complementary feedback clock inpu Differential input FtB OUTT Feedback clock outpu Differential output FtB OUTC Complementary feedback clock outpu Differential output O)E Output Enable (Asynchronous LVCMOS input OVS Output Select (tied to GND or)tLVCMOS inpu DDQ GdND Groun Ground V Logic and output power 1.8V nominal DDQ CsLKT 0:4 Clock output Differential outputs CsLKC 0:4 Complementary clock output Differential outputs NlB No bal The PLL clock buffer, ICS97ULP845A, is designed for a V of 1.8 V, a AV of 1.8 V and differential data input and DDQ DD output levels. Package options include a plastic 28-ball VFBGA. ICS97ULP845A is a zero delay buffer that distributes a differential clock input pair (CLK INT, CLK INC) to five differential pair of clock outputs (CLKT 0:4 , CLKC 0:4 ) and one differential pair feedback clock outputs (FB OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK INT, CLK INC), the feedback clocks (FB INT, FB INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB OUTT/FB OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or V . When OS is high, OE will function as described above. When DDQ OS is low, OE has no effect on CLKT3/CLKC3 (they are free running in addition to FB OUTT/FB OUTC). When AV DD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK INT, CLK INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB INT, FB INC) and the input clock pair (CLK INT, CLK INC) within the specified stabilization time t . STAB The PLL in ICS97ULP845A clock driver uses the input clocks (CLK INT, CLK INC) and the feedback clocks (FB INT, FB INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT 0:4 , CLKC 0:4 ). ICS97ULP845A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. 1109D06/19/07 2